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IEEE 754 Floating Point Pipelined Multiplier with Karatsuba for Mitigations of Area and Power Read chapter Read first chapter

2021 | OriginalPaper | Chapter

Design of a Low-Power Linear Down-Conversion Mixer at 2.45 GHz CMOS 180-nm Technology

Authors : Swarup Dandapat, Shrabanti Das, Moumita Das, Sayan Chatterjee

Published in: Computers and Devices for Communication

Publisher: Springer Singapore

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Abstract

This paper explores the working principles of mixers, which is an integral part of superheterodyne transceiver system. Special emphasis has been led on the design of subharmonic mixers, which is a subclass of the mixer system by using 180-nm CMOS technology. The present paper highlights the design implementation of a 2× subharmonic mixer. From simulation results, it has been observed that the mixer attains 19 dBm IIP3, 12 dB conversion gain, 10 dB noise figure at 2–2.4 GHz RF range and 300–500 MHz of IF range. From 1.8 V supply, total power dissipation has been measured to be 3.8 mW.

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previous chapter Design of a Novel High-Q Active Inductor at 2.5 GHz in CMOS 180-nm Technology
next chapter Comparative Study of AlGaN/GaN HEMT and MOS-HEMT Under Positive Gate Bias-Induced Stress
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Metadata
Title
Design of a Low-Power Linear Down-Conversion Mixer at 2.45 GHz CMOS 180-nm Technology
Authors
Swarup Dandapat
Shrabanti Das
Moumita Das
Sayan Chatterjee
Copyright Year
2021
Publisher
Springer Singapore
Book
Computers and Devices for Communication

Print ISBN: 978-981-15-8365-0

Electronic ISBN: 978-981-15-8366-7

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-15-8366-7_73