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Microsystem Technologies
Published in: Microsystem Technologies 3/2017

11-05-2016 | Technical Paper

Design of an efficient phase frequency detector to reduce blind zone in a PLL

Authors: Umakanta Nanda, Debiprasad Priyabrata Acharya, Sarat Kumar Patra

Published in: Microsystem Technologies | Issue 3/2017

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Abstract

Blind zone of a phase frequency detector (PFD) enhances the phase noise in a Charge Pump PLL. This paper presents a novel technique to reduce the blind zone which reduces the reference spur as well. In this proposed work a variable delay element is incorporated in the Reset path of the PFD. The overall PFD delay is maintained at a small positive value to avoid blind zone at lower phase noise. The performance analysis carried out in Cadence design environment and compared with the performance of a PFD using a fixed delay element in its reset path. The comparison shows that the phase noise is improved by 6 dB.
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Literature
Charles CT, Allstot DJ (2006) A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs. IEEE Trans Circuits Syst II Express Briefs 53(9):822–826CrossRef
Hu W, Chunglen L, Wang X (2007) Fast frequency acquisition phase-frequency detector with zero blind zone in PLL. Electron Lett 43(19):1018–1020CrossRef
Lee W-H, Cho J-D, Lee S-D (1999) A high speed and low power phase-frequency detector and charge-pump. In: Asia and South Pacific IEEE proceedings of the ASP-DAC’99 design automation conference
Lee H, Ahn T, Jung D, Park B (2002) Scheme for no dead zone, fast PFD design. J Korean Phys Soc 40(4):543–545CrossRef
Mansuri M, Liu D, Yang C-KK (2002) Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. IEEE J Solid State Circuits 37(10):1331–1334CrossRef
Tak G-Y, Hyun SB, Kang TY, Choi BG, Park SS (2005) A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications. IEEE J Solid State Circuits 40(8):1671–1679CrossRef
Thompson I, Brennan PV (2003) Phase noise contribution of the phase/frequency detector in a digital PLL frequency synthesiser. IEE Proc Circuits Devices Syst 150(1):1–5CrossRef
W-H Chen, Inerowicz ME, Byunghoo J (2010) Phase frequency detector with minimal blind zone for fast frequency acquisition. IEEE Trans Circuits Syst II Express Briefs 57(12):936–940CrossRef
Xu X, Liu H, Ao S (2011) Design of low phase noise and fast locking PLL frequency synthesizer. In: International conference on electric information and control engineering
Zhang C, Syrzycki M (2010) Modifications of a dynamic-logic phase frequency detector for extended detection range. In: 53rd IEEE international midwest symposium on circuits and systems (MWSCAS)
Metadata
Title
Design of an efficient phase frequency detector to reduce blind zone in a PLL
Authors
Umakanta Nanda
Debiprasad Priyabrata Acharya
Sarat Kumar Patra
Publication date
11-05-2016
Publisher
Springer Berlin Heidelberg
Published in
Microsystem Technologies / Issue 3/2017
Print ISSN: 0946-7076
Electronic ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-016-2970-8

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