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Published in:
2017 | OriginalPaper | Chapter
Design of Quadratic Equations Multiplier (for upto 2-Bit Number) Using Vedic Technique
Authors : Parth Sharma, Raj Pratap Singh, Rohit Singh, Peyush Pande
Published in: Proceeding of International Conference on Intelligent Communication, Control and Devices
Publisher: Springer Singapore
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Abstract
Vedic mathematics is an illustration of 16 mathematical sutras which were introduced by Sri Bharti Krishna Tirthaji. Vedic mathematics defines the distinctive methods of calculation on the basis of 16 sutras. This paper proposes the design of a 2-bit multiplier for multiplying two quadratic equations using Vedic Technique ‘Urdhva Tiryakbhyam’. This paper presents implementation and simulation of Vedic multiplier circuit using Cadence Virtuoso on 180 nm process technology and this is CMOS logic designing. Further, the power consumption of the proposed circuit is also being observed.