Top

Published in:

2014 | OriginalPaper | Chapter

3. DfM at 28 nm and Beyond

Author : Artur Balasinski

Published in: Design for Manufacturability

Publisher: Springer New York

Activate our intelligent search to find suitable subject content or patents.

search-config

AI-assisted search

Off

Abstract

Introduction of more advanced technology nodes carries two key risks:

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

inform now

previous chapter Classic DfM: From 2D to 3D

next chapter New DfM Domain: Stress Effects

Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T., Northrop, G.: Simplify to survive, prescriptive layouts ensure profitable scaling to 32 μm and beyond. In: Proceedings of SPIE, vol. 7275, p. 72750A (March 2009)

Liebmann, L., Baum, Z., Graur, I., Samuels, D.: DFM lessons learned from altPSM design. In: Proceedings of SPIE, 6925, 69250C (2008)

Perez, V., et al.: Convergent automated chip-level lithography checking and fixing at 45 nm. In: Proceedings of SPIE, 7275 (2009)

Hui, C., et al.: Hotspot detection and design recommendation using silicon-calibrated CMP model. In: Proceedings of SPIE, 7275 (2009)

Liebmann, L.: Layout impact of resolution enhancement techniques: impediment or opportunity? In: ISPD’03, Monterey (2003)

Webb, C.: Intel design for manufacturing and evolution of design rules. Proc. SPIE 6925, 692503 (2008)CrossRef

Pileggi, L., Strojwas, A.J.: Regular fabrics for nano-scaled CMOS technologies. In: Proceedings of ISSCC (2006)

Jhaveri, T., et al.: Maximization of layout printability/manufacturability by extreme layout regularity. Micro Nanolithogr. MEMS MOEMS 6(03), 031011–033000 (2007)CrossRef

Abercrombie, D., Elakkumanan, P., Liebmann, L.: Restrictive design rules and their impact on 22 nm design and physical verification, EDPS2009 (2009)

10.

Volkov, A., Routing Technologies for 28 nm and beyond, Chip Design Magazine, Summer 2011

11.

White Paper: Tips and techniques for 28 nm design optimization, Altera Corporation, November 2011

12.

Beylier, C., Moyroud, C., Granger, F.B., Robert, F., Yesilada, E., Trouiller, Y., Marin, J.-C.: Fully integrated litho aware PnR design solution. Proc. SPIE 8327, 83270A (2012)CrossRef

13.

Hurley, P., Kryszczull, K.: Replacing design rules in the VLSI Design Cycle, Proc. of SPIE 8327, 83270B1–B6 (2012)CrossRef

14.

Dai, V., Capodicci, L., Yang, J., Rodriguez, N.: Developing DRC plus through 2D pattern extraction and clustering techniques. Proc. SPIE 7275, 727517 (2009)CrossRef

15.

Russel, P.: Norvig, Artificial Intelligence. A Modern Approach. Prentice Hall, Englewood Cliffs (1995)

16.

Duda, R.O., Hart, P.E., Stork, D.G.: Pattern Classification. Wiley, New York (2001)MATH

17.

Mitchell, T.M.: Machine Learning. Mc Graw Hill, New York (1997)MATH

18.

Cao, Y., Lu, Y.-W., Chen, L., Ye, J.: Optimized hardware and software for fast, full chip simulation. Proc. SPIE 5754, 407–414 (2005)CrossRef

19.

Jang, J.: Manufacturability aware design. Ph.D. thesis, The University of Michigan (2007)

20.

Taur, Y., Ning, T.H.: Fundamentals of Modern VLSI Devices. Cambridge University Press (1998)

21.

Pileggi, L., Schmit, H., Strojwas, A.J., et al.: Exploring regular fabrics to optimize the performance-cost trade-off. In: Proceedings of the ACM/IEEE DAC (2003)

22.

Webb, C.: Layout rule trends and affect upon CPU design, design and process integration for microectronic manufacturing IV. In: Wong, A.K.K., Singh, V.K. (eds) Proceedings of SPIE, 6156, 615602 (2006)

23.

Eclair Pattem Matcher End User’s Guide, Version 5.0, CommandCAD, Inc., March 2006

24.

Yang, J., Cohen, E., Tabery, C., Rodriguez, N., Craig, M.: An up-stream design auto-fix flow for manufacturability enhancement. In: 43rd Design Automation Conference (2006)

25.

Torres, J.A., Berglund, N.C.: Towards manufacturability closure process variations and layout design. In: IEEE EDPS Workshop (2005)

26.

Torre, J.A.: Litho-friendly design: a necessary complement to RET. Microlithogr. World 15(2), 10–13 (2006). 12-13AMathSciNet

27.

Strojwas, A.: Cost effective scaling to 22 nm and below technology nodes. In: VLSI Technology, Systems and Applications, pp 1–2 (2011)

28.

Hoppe, W., Roessler, T., Torres, J.A.: Beyond rule-based physical verification. In: Proceedings of SPIE, 6349(190) (2006)

29.

Chiang, C., Kawa, J.: Three DfM challenges: random defects, thickness variation, and printability variation. In: IEEE Asia Pacific Conference on Circuits and Systems, 2006. APCCAS 2006, p.1099, 4–7 Dec 2006

30.

Peter, K., März, R., Gröndahl, S.: Litho-friendly design (LFD) methodologies applied to library cells. Proc. SPIE 6349(14), 63490E (2006)CrossRef

31.

Capodieci, L.: From optical proximity correction to lithography-driven physical design (1996–2006): 10 years of resolution enhancement technology and the roadmap enablers for the next decade, optical microlithography XIX. In: Flagello, D.G. (ed) Proceedings of SPIE, 6154, 615401 (2006)

32.

Gianfagna, M., Liebmann, L., Pileggi, L., Hibbeler, J., Rovner, V., Jhaveri, T.: Greg Northrop, Private Communication

33.

Jang, D. et al.: DFM optimization of standard cells considering random and systematic defect. In: ISOCC (2008)

34.

Paek, S.W., Kang, J.H., Ha, N., Kim, B.M., Jang, D.H., Jeon, J., Kim, D.W., Chung, K.Y., Yu, S., Park, J.H., Bae s., Song, D., Noh, W., Kim, Y.D., Song, H.S., Choi, H.B., Kim, K.S., Choi, K.M., Choi, W.C., Jeon, J.W., Lee, J.W., Kim, K.S., Park, S.H., Chung, N.Y., Lee, K.D., Hong, Y.K., Kim, B.S.: Yield enhancement with DFM, Design for manufacturability through design-process integration VI. In: Mason, M.E., Sturtevant, J.L. (eds) Proceedings of SPIE, 8327, 832704 (2012)

35.

TSMC Open Innovation Platform: www.tsmc.com.tw (2011)

36.

Paek, S.W., Jang, D.H., Park, J.H., Ha, N., Kim, B.M., et al.: Enhanced layout optimization of sub-45 nm standard: memory cells. SPIE, 7725, 72751M (2009)

37.

Kahng, A.B., Samadi, K.: CMP fill synthesis: a survey of recent studies. IEEE Trans. Comp. Aid. Design 27(1), 3–19 (2008)CrossRef

38.

Simmons, M.C., Kang, J.H., Kim, Y., et al.: A state-of-the-art hotspot recognition system for full chip verification with lithographic simulation. SPIE, 7974, 79740M (2011)

39.

Ha, N., Lee, J., Paek, S.W. et al.: In-design DFM CMP flow for block level simulation using 32 nm CMP model. SPIE, 7974, 79740W (2011)

40.

Drennan, P.G., Kniffin, M.L., Locascio, D.R.: Implications of proximity Effects for Analog Design, IEEE CICC (2006)

41.

Postnikow, S., Hector, S.: ITRS CD error budgets: proposed simulation study methodology. In: International Technology Roadmap for Semiconductors, May (2003)

42.

Tabery, C., Page, L.: Use of design pattern layout for automated metrology recipe generation. In: Proceedings of SPIE: Metrology, Inspection and Process Control for Microlithography XIX, vol. 5752, pp. 1424–1434 (2005)

43.

Hook, T., et al.: The dependence of channel length on channel width in narrow-channel CMOS devices for 0.25–0.13 μm technologies. IEEE Electron. Device. Lett. 21(2), 85–87 (2000)CrossRef

44.

Su, K.W., et al.: A scalable model for STI mechanical stress effect on layout dependence of MOS electrical characterization. In: IEEE CICC, pp. 245–248 (2003)

45.

Scott, G., et al.: NMOS drive current reduction caused by transistor layout and trench isolation induced stress. In: IEEE IEDM, pp. 827–830 (1999)

46.

Bianchi, R.A., et al.: Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical performance. In: IEEE IEDM, pp. 117–120 (2002)

47.

Miyamoto, M., et al.: Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics. IEEE Trans. Electron. Devices. 51, 440–443 (2004)CrossRef

48.

Choi, Y.S., Lian, G., Olubuigde, O., Chung, J., Riley, D., Baldwin, G.: Layout variation Effects in Advanced MOSFECTs: STI-Induced Embedded Sige strain Relaxation and Dual Stress Liner Boundary Proxinuty Effect. IEEE Trans. Electron. Devices. 57(11), 2886–2890 (2010)CrossRef

49.

Hook, T.H., et al.: Lateral ion implant straggle and mask proximity effect. IEEE Trans. Electron. Devices. 50, 1946–1951 (2003)CrossRef

50.

Sheu, Y.M., et al.: Modeling well edge proximity effect on highly-scaled MOSFETs. In: IEEE CICC, pp. 831–834 (2005)

51.

Kumar, D.V., et al.: Evaluation of the impact of layout on device and analog circuit performance with lateral asymmetric channel MOSFETs. IEEE Trans. Electron. Devices 52, 1603–1609 (2005)CrossRef

52.

Enemon, G., Verheyen, P., De Keersgieter, A., Jurczak, M., de Meyer, K.: Scalability of stress induced by contact-etch-stop layers: a simulation study. IEEE Trans. Electron. Device 54(6), 1446 (2007)CrossRef

Title: DfM at 28 nm and Beyond
Author: Artur Balasinski
Publisher: Springer New York
Book: Design for Manufacturability
Print ISBN: 978-1-4614-1760-6

Electronic ISBN: 978-1-4614-1761-3

Copyright Year: 2014
DOI: https://doi.org/10.1007/978-1-4614-1761-3_3