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Published in: Journal of Electronic Testing 1/2020

20-03-2020

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

Authors: Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik

Published in: Journal of Electronic Testing | Issue 1/2020

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Abstract

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

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Appendix
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Metadata
Title
High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors
Authors
Adeboye Stephen Oyeniran
Raimund Ubar
Maksim Jenihhin
Jaan Raik
Publication date
20-03-2020
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 1/2020
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05856-7

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