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Journal of Electronic Testing
Published in: Journal of Electronic Testing 1/2020

03-02-2020

Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures

Authors: Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal

Published in: Journal of Electronic Testing | Issue 1/2020

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Abstract

This article analyzes and rationalizes the capabilities of inversion test points (TPs) when implemented in lieu of traditional test point architectures. With scaling transistor density, logic built-in self-test (LBIST) quality degrades and additional efforts must keep LBIST quality high. Additionally, delay faults must be targeted by LBIST, but delay faults can be masked when using control-0/1 (i.e., traditional) TP architectures. Although inversions as TPs have been proposed in literature, the effect inversion TPs have on fault coverage compared to traditional alternatives has not been explored. This study extends work previously presented in the North Atlantic Test Workshop (NATW’19) and finds both stuck-at and delay fault coverage improves under pseudo-random tests using inversion TPs, and extended data collection finds noteworthy trends on the effectiveness of TP architectures.
previous article An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits
next article An Efficient Accuracy Reconfigurable CLA Adder Designs Using Complementary Logic

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Literature
1.
Abramovici M, Breuer MA (1979) On redundancy and fault detection in sequential circuits. IEEE Transactions on Computers C-28(11):864–865MathSciNetCrossRef
2.
Acero C, Feltham D, Liu Y, Moghaddam E, Mukherjee N, Patyra M, Rajski J, Reddy SM, Tyszer J, Zawada J (2017) Embedded deterministic test points. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25(10):2949–2961CrossRef
3.
Bakshi D (2012) Techniques for seed computation and testability enhancement for logic built-in self test. Master’s thesis, Virginia Tech
4.
Bardell PH, McAnney WH, Savir J (1987) Built-in test for VLSI: pseudorandom techniques. Wiley-Interscience, New York
5.
Brglez F (1984) On testability analysis of combinational networks. In: Proceedings of the international symposium on circuits and systems (ISCAS), vol 1, pp 221–225
6.
Brglez F, Fujiwara H (1985) A neutral netlist of 10 combinational benchmark circuits and a targeted translator in fortran. In: Proceedings of the IEEE Int. symposium on circuits and systems (ISCAS), pp 677–692
7.
Briers AJ, Totton KAE (1986) Random pattern testability by fast fault simulation. In: Proceedings of IEEE international test conference (ITC)
8.
Cheng K-T, Lin C-J (1995) Timing-driven test point insertion for full-scan and partial-scan BIST. In: Proceedings of the IEEE international test conference (ITC), pp 506–514
9.
Corno F, Reorda MS, Squillero G (2000) RT-level ITC’99 benchmarks and first ATPG results. IEEE Design & Test of Computers 17(3):44–53CrossRef
10.
David R (1986) Signature analysis for multiple-output circuits. IEEE Trans Comput 35(9):830–837CrossRef
11.
Dervisoglu BI, Stong GE (1991) Design for testability using scanpath techniques for path-delay test and measurement. In: Proc IEEE International Test Conference, pp 365–374
12.
Fang Y, Albicki A (1995) Efficient testability enhancement for combinational circuit. In: Proceedings of international conference on computer design (ICCD), pp 168–172
13.
Geuzebroek MJ, van der Linden JT, van de Goor AJ (2002) Test point insertion that facilitates ATPG in reducing test time and data volume. In: Proceedings of the IEEE international test conference, Washington, DC, USA, pp 138–147
14.
Ghani T, Mistry K, Packan P, Thompson S, Stettler M, Tyagi S, Bohr M (2000) Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors. In: Proc Symposium on VLSI Technology, pp 174–175
15.
Hayes JP, Friedman AD (1974) Test point placement to simplify fault detection. IEEE Trans Comput C-23(7):727–735CrossRef
16.
He M, Gustavo K, Contreas, Tran D, Winemberg L, Tehranipoor M (2017) Test-point insertion efficiency analysis for LBIST in high-assurance applications. IEEE Transactions on Very Large Scale Integration 25(9)
17.
Higgins FP, Srinivasan R (2000) BSM2: Next generation boundary-scan master. In: Proc 18th IEEE VLSI Test Symposium (VTS), pp 67–72
18.
Iyengar VS, Brand D (1989) Synthesis of pseudo-random pattern testable designs. In: Proceedings of the international test conference, pp 501–508
19.
Karpovsky MG, Gupta SK, Pradhan DK (1991) Aliasing and diagnosis probability in misr and stumps using a general error model. In: Proceedings of the international test conference, Nashville, TN, pp 828–839
20.
Mahmod J, Millican SK, Guin U, Agrawal VD (2019) Special session: delay fault testing - present and future. Proceedings of the 37th VLSI Test Symposium (VTS), Monterey, CA
21.
Majhi AK, Agrawal VD (1998) Delay fault models and coverage. In: Proc 11th international conference on VLSI Design, Chennai, India, pp 364–369
22.
Makar SR, McCluskey EJ (1995) Functional tests for scan chain latches. In: Proceedings of international test conference (ITC), pp 606–615
23.
Mattiuzzo R, Appello D, Allsup C (2009) Small-delay-defect testing. EDN (Electrical Design News) 54 (13):28
24.
25.
Nag PK, Gattiker A, Wei S, Blanton RD, Maly W (2002) Modeling the economics of testing: a DFT perspective. IEEE Design & Test of Computers 19(1):29–41CrossRef
26.
Nigh P, Needham W, Butler K, Maxwell P, Aitken R (1997) An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. In: Proc 15th IEEE VLSI Test Symposium, pp 459–464
27.
Pateras S (2003) Achieving at-speed structural test. IEEE Design and Test of Computers 20(5):26–33CrossRef
28.
Rajski J, Tyszer J (1998) Arithmetic built-in self-test for embedded systems. Prentice-Hall Inc., Upper Saddle RiverMATH
29.
Ren H, Kusko M, Kravets V, Yaari R (2009) Low cost test point insertion without using extra registers for high performance design. In: Proceedings of the International Test Conference (ITC), Austin, TX
30.
Roy S, Stiene B, Millican SK, Agrawal VD (2019) Improved random pattern delay fault coverage using inversion test points. In: IEEE 28th North Atlantic Test Workshop (NATW), pp 206–211
31.
Rudnick EM, Chickermane V, Patel JH (1994) An observability enhancement approach for improved testability and at-speed test. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13 (8):1051–1056CrossRef
32.
Savaria Y, Youssef M, Kaminska B, Koudil M (1991) Automatic test point insertion for pseudo-random testing. In: Proceedings of the IEEE international sympoisum on circuits and systems (ISCAS), vol 4, pp 1960–1963
33.
Sayil S (2018) Conventional test methods. In: Contactless VLSI measurement and testing techniques. Springer, pp 1–7
34.
Sootkaneung W, Howimanporn S, Chookaew S (2018) Temperature effects on BTI and soft errors in modern logic circuits. Microelectronics Reliability 87:259–270CrossRef
35.
Takeda E, Suzuki N (1983) An empirical model for device degradation due to hot-carrier injection. IEEE Electron Device Letters 4(4):111–113CrossRef
36.
Tamarapalli N, Rajski J (1996) Constructive multi-phase test point insertion for scan-based bist. In: Proceedings of the International Test Conference (ITC), pp 649–658
37.
Touba NA, McCluskey EJ (1994) Automated logic synthesis of random pattern testable circuits. In: Proceedings of the IEEE international test conference (ITC), pp 174–183
38.
Tsai HC, Cheng K-T, Lin CJ, Bhawmik S (1997) A hybrid algorithm for test point selection for scan-based BIST. In: Proceedings of the 34th design automation conference (DAC), pp 478–483
39.
Xiang D, Wen X, Wang L (2017) Low-power scan-based built-in self-test based on weighted pseudorandom test pattern generation and reseeding. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (3):942–953CrossRef
40.
Yang J, Touba NA, Nadeau-Dostie B (2012) Test point insertion with control points driven by existing functional flip-flops. IEEE Trans Comput 61(10):1473–1483MathSciNetCrossRef
41.
Youssef M, Savaria Y, Kaminska B (1993) Methodology for efficiently inserting and condensing test points (cmos ics testing). IEE Proceedings-E (Computers and Digital Techniques) 140(3):154–160CrossRef
Metadata
Title
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures
Authors
Soham Roy
Brandon Stiene
Spencer K. Millican
Vishwani D. Agrawal
Publication date
03-02-2020
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 1/2020
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-020-05859-4

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