High Performance Modified Static Segment Approximate Multiplier based on Significance Probability

Achieving high accuracy has become a key design objective in high quantity digital data computing devices. To enhance the accuracy, a high performance Modified Static Segment approximate Multiplier (MSSM) is proposed in this paper. It increases the accuracy based on the negating lower order significant information of input operands using Significance Estimator Logic Circuit (SELC). The performance of proposed MSSM is compared with the existing approximate multipliers such as a Dynamic Segment approximate Multiplier (DSM) and Static Segment approximate Multiplier (SSM) for all input combinations. These multipliers are implemented and simulated using Xilinx 14.2 ISE. In MSSM method, 99% of average computational accuracy can be achieved for a 16-bit multiplication even with an 8 × 8-bit multiplier from all combinations of input operands instead of 95% of average computational accuracy from 61% of input operand pair in the existing SSM method. The proposed 16-bit MSSM offers a savings of 83.45% LUTs, 38.78% power and it exhibits 24.40% less delay, 0.6% less computational accuracy than the existing DSM.