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Published in: Journal of Computational Electronics 3/2017

13-05-2017

New technique to extend the vertical depletion region at SOI-LDMOSFETs

Authors: Hojjat Allah Mansoori, Ali A. Orouji, A. Dideban

Published in: Journal of Computational Electronics | Issue 3/2017

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Abstract

In order to obtain an excellent performance for silicon-on-insulator lateral double-diffused MOSFET (SOI-LDMOSFET) transistors, we introduce a new technique to extend the depletion region along the vertical direction in the drift region. The proposed structure is called vertically depleted LDMOSFET (VD-LDMOSFET). The VD-LDMOSFET structure consists of a buried metal layer in the oxide region. The drift region of the VD-LDMOSFET is vertically depleted, not only from the buried oxide, but also by the incorporated metal layer in the buried oxide. Therefore, a higher drift doping density is achieved by an extension of the depletion region in the drift region and the on-state resistance \(({R}_{\mathrm{ON}})\) reduces without degradation of the breakdown voltage. Also, an additional peak is created in the electric field distribution of the proposed structure and causes a reduction of the electric field peak near the gate and the drift region junction at the top surface of the device. Therefore, the breakdown voltage \(({V}_{\mathrm{BR}})\) of the VD-LDMOSFET structure increases. The simulation results illustrate that by optimizing the doping density of the drift region and the dimensions of the metal layer in the proposed structure, the on-state resistance (28.9%) and the breakdown voltage (36.1%) are improved greatly and a superior tradeoff is achieved compared with a conventional SOI-LDMOSFET (C-LDMOSFET) structure.

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Literature
1.
go back to reference Zitouni, M., Morancho, F., Rossel, P., Tranduc, H., Buxo, J., Pages, I.: A new concept for the lateral DMOS transistor for smart power IC’s, Proceedings., The 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD ’99, pp. 73–76, (1999) Zitouni, M., Morancho, F., Rossel, P., Tranduc, H., Buxo, J., Pages, I.: A new concept for the lateral DMOS transistor for smart power IC’s, Proceedings., The 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD ’99, pp. 73–76, (1999)
2.
go back to reference Hu, Y., Huang, Q., Wang, G., Chang, S., Wang, H.: A novel high-voltage (\(>\) 600 V) LDMOSFET with buried N-layer in partial SOI technology. IEEE Trans. Electron Devices 59(4), 1131–1136 (2012)CrossRef Hu, Y., Huang, Q., Wang, G., Chang, S., Wang, H.: A novel high-voltage (\(>\) 600 V) LDMOSFET with buried N-layer in partial SOI technology. IEEE Trans. Electron Devices 59(4), 1131–1136 (2012)CrossRef
3.
go back to reference Cao, G., Manhas, S.K., Narayanan, E.M.S., De Souza, M.M., Hinchley, D.: Comparative study of drift region designs in RF LDMOSFETs. IEEE Trans. Electron Devices 51(8), 1296–1303 (2004)CrossRef Cao, G., Manhas, S.K., Narayanan, E.M.S., De Souza, M.M., Hinchley, D.: Comparative study of drift region designs in RF LDMOSFETs. IEEE Trans. Electron Devices 51(8), 1296–1303 (2004)CrossRef
4.
go back to reference Arnold, E.: Silicon-on-insulator devices for high voltage and power IC applications. J. Electrochem. Soc. 141(7), 1983–1988 (1994)CrossRef Arnold, E.: Silicon-on-insulator devices for high voltage and power IC applications. J. Electrochem. Soc. 141(7), 1983–1988 (1994)CrossRef
5.
go back to reference Fiorenza, J.G., Del Alamo, J.A.: Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon. IEEE Trans. Electron Devices 49(4), 687–692 (2002)CrossRef Fiorenza, J.G., Del Alamo, J.A.: Experimental comparison of RF power LDMOSFETs on thin-film SOI and bulk silicon. IEEE Trans. Electron Devices 49(4), 687–692 (2002)CrossRef
6.
go back to reference Luo, X., Zhang, B., Li, Z.: A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer. Solid. State. Electron. 51(3), 493–499 (2007)CrossRef Luo, X., Zhang, B., Li, Z.: A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer. Solid. State. Electron. 51(3), 493–499 (2007)CrossRef
7.
go back to reference Xia, C., Cheng, X., Wang, Z., Cao, D., Jia, T., Zheng, L., Yu, Y., Shen, D.: A novel partial-SOI LDMOSFET (\(>\)800 V) with n-type floating buried layer in substrate. Microelectron. Reliab. 54(3), 582–586 (2014)CrossRef Xia, C., Cheng, X., Wang, Z., Cao, D., Jia, T., Zheng, L., Yu, Y., Shen, D.: A novel partial-SOI LDMOSFET (\(>\)800 V) with n-type floating buried layer in substrate. Microelectron. Reliab. 54(3), 582–586 (2014)CrossRef
8.
go back to reference Luo, J., Cao, G., Ekkanath Madathil, S.N., De Souza, M.M.: A high performance RF LDMOSFET in thin film SOI technology with step drift profile. Solid. State. Electron. 47(11), 1937–1941 (2003)CrossRef Luo, J., Cao, G., Ekkanath Madathil, S.N., De Souza, M.M.: A high performance RF LDMOSFET in thin film SOI technology with step drift profile. Solid. State. Electron. 47(11), 1937–1941 (2003)CrossRef
9.
go back to reference Wang, Z., Cheng, X., He, D., Xia, C., Xu, D., Yu, Y., Zhang, D., Wang, Y., Lv, Y., Gong, D., Shao, K.: Realization of 850 V breakdown voltage LDMOS on Simbond SOI. Microelectron. Eng. 91, 102–105 (2012)CrossRef Wang, Z., Cheng, X., He, D., Xia, C., Xu, D., Yu, Y., Zhang, D., Wang, Y., Lv, Y., Gong, D., Shao, K.: Realization of 850 V breakdown voltage LDMOS on Simbond SOI. Microelectron. Eng. 91, 102–105 (2012)CrossRef
10.
go back to reference Kim, I.J., Matsumoto, S., Sakai, T., Yachi, T.: Breakdown voltage improvement for thin-film SOI power MOSFET’s by a buried oxide step structure. IEEE Electron Device Lett. 15(5), 148–150 (1994)CrossRef Kim, I.J., Matsumoto, S., Sakai, T., Yachi, T.: Breakdown voltage improvement for thin-film SOI power MOSFET’s by a buried oxide step structure. IEEE Electron Device Lett. 15(5), 148–150 (1994)CrossRef
11.
go back to reference Mahabadi, S.J., Orouji, A.A., Keshavarzi, P., Moghadam, H.A.: A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage. Semicond. Sci. Technol. 26(9), 095005 (2011)CrossRef Mahabadi, S.J., Orouji, A.A., Keshavarzi, P., Moghadam, H.A.: A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage. Semicond. Sci. Technol. 26(9), 095005 (2011)CrossRef
12.
go back to reference Mehrad, M., Orouji, A.A.: A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature. Mater. Sci. Semicond. Process. 16(6), 1977–1981 (2013)CrossRef Mehrad, M., Orouji, A.A.: A novel high voltage lateral double diffused metal oxide semiconductor (LDMOS) device with a U-shaped buried oxide feature. Mater. Sci. Semicond. Process. 16(6), 1977–1981 (2013)CrossRef
13.
go back to reference Goyal, N., Saxena, R.S.: A new LDMOSFET with tunneling junction for improved on-state performance. IEEE Electron Device Lett. 34(1), 90–92 (2013)CrossRef Goyal, N., Saxena, R.S.: A new LDMOSFET with tunneling junction for improved on-state performance. IEEE Electron Device Lett. 34(1), 90–92 (2013)CrossRef
14.
go back to reference Wu, W., Zhang, B., Luo, X., Li, Z.: Low specific on-resistance power MOSFET with a surface improved super-junction layer. Superlattices Microstruct. 72, 1–10 (2014)CrossRef Wu, W., Zhang, B., Luo, X., Li, Z.: Low specific on-resistance power MOSFET with a surface improved super-junction layer. Superlattices Microstruct. 72, 1–10 (2014)CrossRef
15.
go back to reference Duan, B., Zhang, B., Li, Z.: New thin-film power MOSFETs with a buried oxide double step structure. IEEE Electron Device Lett. 27(5), 377–379 (2006)CrossRef Duan, B., Zhang, B., Li, Z.: New thin-film power MOSFETs with a buried oxide double step structure. IEEE Electron Device Lett. 27(5), 377–379 (2006)CrossRef
16.
go back to reference Kumar, M.J., Sithanandam, R.: Extended-p\(^{+}\) stepped gate LDMOS for improved performance. IEEE Trans. Electron Devices 57(7), 1719–1724 (2010)CrossRef Kumar, M.J., Sithanandam, R.: Extended-p\(^{+}\) stepped gate LDMOS for improved performance. IEEE Trans. Electron Devices 57(7), 1719–1724 (2010)CrossRef
17.
go back to reference Orouji, A.A., Mansoori, H.A., Dideban, A., Shahnazarisani, H.: A novel LDMOS structure using P-trench for high performance applications. Mater. Sci. Semicond. Process. 39, 654–658 (2015)CrossRef Orouji, A.A., Mansoori, H.A., Dideban, A., Shahnazarisani, H.: A novel LDMOS structure using P-trench for high performance applications. Mater. Sci. Semicond. Process. 39, 654–658 (2015)CrossRef
18.
go back to reference Orouji, A.A., Hanaei, M.: A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines. Phys. E Low-dimens. Syst. Nanostruct. 74, 297–302 (2015)CrossRef Orouji, A.A., Hanaei, M.: A novel lateral diffused metal oxide semiconductor (LDMOS) by attracting the electric field Lines. Phys. E Low-dimens. Syst. Nanostruct. 74, 297–302 (2015)CrossRef
20.
go back to reference Maleville, C., Mazuré, C.: Smart-Cut technology: from 300 mm ultrathin SOI production to advanced engineered substrates. Solid. State. Electron. 48(6), 1055–1063 (2004)CrossRef Maleville, C., Mazuré, C.: Smart-Cut technology: from 300 mm ultrathin SOI production to advanced engineered substrates. Solid. State. Electron. 48(6), 1055–1063 (2004)CrossRef
21.
go back to reference Ramezani, Z., Orouji, A.A.: Amended electric field distribution: a reliable technique for electrical performance improvement in nano scale SOI MOSFETs. J. Electron. Mater. 46(4), 2269–2281 (2017)CrossRef Ramezani, Z., Orouji, A.A.: Amended electric field distribution: a reliable technique for electrical performance improvement in nano scale SOI MOSFETs. J. Electron. Mater. 46(4), 2269–2281 (2017)CrossRef
22.
go back to reference Yang, F., Gong, J., Su, R., Huo, K., Tsai, C., Cheng, C., Liou, R., Tuan, H., Huang, C.: A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA. IEEE Trans. Electron Devices 60(9), 2847–2853 (2013)CrossRef Yang, F., Gong, J., Su, R., Huo, K., Tsai, C., Cheng, C., Liou, R., Tuan, H., Huang, C.: A 700-V device in high-voltage power ICs with low on-state resistance and enhanced SOA. IEEE Trans. Electron Devices 60(9), 2847–2853 (2013)CrossRef
23.
go back to reference Aminbeidokhti, A., Orouji, A.A., Rahmaninezhad, S., Ghasemian, M.: A novel high-breakdown-voltage SOI MESFET by modified charge distribution. IEEE Trans. Electron Devices 59(5), 1255–1262 (2012)CrossRef Aminbeidokhti, A., Orouji, A.A., Rahmaninezhad, S., Ghasemian, M.: A novel high-breakdown-voltage SOI MESFET by modified charge distribution. IEEE Trans. Electron Devices 59(5), 1255–1262 (2012)CrossRef
24.
go back to reference Orouji, A.A., Sharbati, S., Fathipour, M.: A new partial-SOI LDMOSFET with modified electric field for breakdown voltage improvement. IEEE Trans. Device Mater. Reliab. 9(3), 449–453 (2009)CrossRef Orouji, A.A., Sharbati, S., Fathipour, M.: A new partial-SOI LDMOSFET with modified electric field for breakdown voltage improvement. IEEE Trans. Device Mater. Reliab. 9(3), 449–453 (2009)CrossRef
25.
go back to reference Chang, Y., Lin, S., Chang, C.: Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate. Microelectron. Reliab. 50(7), 949–953 (2010)CrossRef Chang, Y., Lin, S., Chang, C.: Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate. Microelectron. Reliab. 50(7), 949–953 (2010)CrossRef
Metadata
Title
New technique to extend the vertical depletion region at SOI-LDMOSFETs
Authors
Hojjat Allah Mansoori
Ali A. Orouji
A. Dideban
Publication date
13-05-2017
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 3/2017
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-017-0994-7

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