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A Robust Architecture Based on Adaptive Recursive Filter for Gigabit Communications Read chapter Read first chapter

2021 | OriginalPaper | Chapter

Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm

Authors : K. V. Gowreesrinivas, P. Samundiswary

Published in: Microelectronics, Electromagnetics and Telecommunications

Publisher: Springer Singapore

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Abstract

The execution of multiplication consumes more time, power and also requires more area than other arithmetic operations. Hence, in floating-point multiplication, performance-optimized mantissa multiplication is necessary to get efficient response. In this paper, unified adder–subtractor-based 24-bit mantissa multiplication is designed. First, single precision floating-point multiplication is designed with Karatsuba algorithm to improve the speed, and later for more better performance, an unified adder–subtractor-based carry-select adder is introduced in Karatsuba algorithm. In this, Karatsuba algorithm is developed by using Vedic multiplication along with unified adder–subtractor logic. Further, the performance metrics are analyzed for the existing techniques with the proposed techniques. All modules are developed with Xilinx ISE.

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Metadata
Title
Performance Efficient Floating-Point Multiplication Using Unified Adder–Subtractor-Based Karatsuba Algorithm
Authors
K. V. Gowreesrinivas
P. Samundiswary
Copyright Year
2021
Publisher
Springer Singapore
Book
Microelectronics, Electromagnetics and Telecommunications

Print ISBN: 978-981-15-3827-8

Electronic ISBN: 978-981-15-3828-5

Copyright Year: 2021

DOI
https://doi.org/10.1007/978-981-15-3828-5_51