Skip to main content
Top

2017 | OriginalPaper | Chapter

8. Security Down to the Hardware Level

Authors : Anastacia Alvarez, Massimo Alioto

Published in: Enabling the Internet of Things

Publisher: Springer International Publishing

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

This chapter introduces the concept of Physically Unclonable Functions (PUFs), their prospects for hardware security in IoT devices, and their interaction with traditional cryptography. Section 8.1 summarizes the background on PUFs, whereas Sect. 8.2 covers the metrics that are commonly used to evaluate PUF performance. Such metrics are used to comparatively review the state of the art on PUFs in Sect. 8.3. Section 8.4 covers vulnerabilities to malicious attacks attempting to clone or mimic a PUF. In the last section, we introduce the novel concept of PUF-enhanced cryptography as a promising direction aiming to merge PUFs and cryptography in a cohesive framework for IoT hardware-level security.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literature
go back to reference M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits. IEEE Trans. Circuits Syst. I 57(2), 355–367 (2010a)MathSciNetCrossRef M. Alioto, L. Giancane, G. Scotti, A. Trifiletti, Leakage power analysis attacks: a novel class of attacks to nanometer cryptographic circuits. IEEE Trans. Circuits Syst. I 57(2), 355–367 (2010a)MathSciNetCrossRef
go back to reference M. Alioto, M. Poli, S. Rocchi, Differential power analysis attacks to precharged buses: a general analysis for symmetric-key cryptographic algorithms. IEEE Trans. Dependable Secur. Comput. 7(3), 226–239 (2010b)CrossRef M. Alioto, M. Poli, S. Rocchi, Differential power analysis attacks to precharged buses: a general analysis for symmetric-key cryptographic algorithms. IEEE Trans. Dependable Secur. Comput. 7(3), 226–239 (2010b)CrossRef
go back to reference M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, A. Trifiletti, Effectiveness of leakage power analysis attacks on DPA-resistant logic styles under process variations. IEEE Trans. Circuits Syst. I Regul. Pap. 61(2), 429–442 (2014)CrossRef M. Alioto, S. Bongiovanni, M. Djukanovic, G. Scotti, A. Trifiletti, Effectiveness of leakage power analysis attacks on DPA-resistant logic styles under process variations. IEEE Trans. Circuits Syst. I Regul. Pap. 61(2), 429–442 (2014)CrossRef
go back to reference A. Alvarez, W. Zhao, M. Alioto, 15 fJ/bit static physically unclonable functions for secure chip identification with <2% native bit instability and 140x inter/intra puf hamming distance separation in 65 nm. IEEE Int. Solid-State Circuits Conf. 5, 256–258 (2015) A. Alvarez, W. Zhao, M. Alioto, 15 fJ/bit static physically unclonable functions for secure chip identification with <2% native bit instability and 140x inter/intra puf hamming distance separation in 65 nm. IEEE Int. Solid-State Circuits Conf. 5, 256–258 (2015)
go back to reference A.B. Alvarez, W. Zhao, M. Alioto, Static physically unclonable functions for secure chip identification with 1.9–5.8% native bit instability at 0.6–1 V and 15fJ/bit in 65 nm. IEEE J. Solid State Circuits 60(5), 1–4 (2016) A.B. Alvarez, W. Zhao, M. Alioto, Static physically unclonable functions for secure chip identification with 1.9–5.8% native bit instability at 0.6–1 V and 15fJ/bit in 65 nm. IEEE J. Solid State Circuits 60(5), 1–4 (2016)
go back to reference A. Aysu, P. Schaumont, Precomputation methods for hash-based signatures on energy-harvesting platforms. IEEE Trans. Comput. 65(9), 2925–2931 (2016)MathSciNetCrossRef A. Aysu, P. Schaumont, Precomputation methods for hash-based signatures on energy-harvesting platforms. IEEE Trans. Comput. 65(9), 2925–2931 (2016)MathSciNetCrossRef
go back to reference M. Bhargava, K. Mai, An efficient reliable PUF-based cryptographic key generator in 65 nm CMOS. Design Autom. Test Europe Conf. Exhibition 1, 1–6 (2014) M. Bhargava, K. Mai, An efficient reliable PUF-based cryptographic key generator in 65 nm CMOS. Design Autom. Test Europe Conf. Exhibition 1, 1–6 (2014)
go back to reference M. Bhargava, C. Cakir, K. Mai, Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2010) pp. 106–111 M. Bhargava, C. Cakir, K. Mai, Attack resistant sense amplifier based PUFs (SA-PUF) with deterministic and controllable reliability of PUF responses, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2010) pp. 106–111
go back to reference C. Bösch, J. Guajardo, A.R. Sadeghi, J. Shokrollahi, P. Tuyls, Efficient helper data key extractor on FPGAs. Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics) 5154 LNCS, 181–197 (2008) C. Bösch, J. Guajardo, A.R. Sadeghi, J. Shokrollahi, P. Tuyls, Efficient helper data key extractor on FPGAs. Lect. Notes Comput. Sci. (including Subser. Lect. Notes Artif. Intell. Lect. Notes Bioinformatics) 5154 LNCS, 181–197 (2008)
go back to reference E. Brier, C. Clavier, F. Olivier, Correlation power analysis with a leakage model, in Cryptographic Hardware and Embedded Systems (2004), pp. 16–29 E. Brier, C. Clavier, F. Olivier, Correlation power analysis with a leakage model, in Cryptographic Hardware and Embedded Systems (2004), pp. 16–29
go back to reference D. Canright, L. Batina, A very compact ‘perfectly masked’ S-box for AES, in Lecture Notes in Computer Science (2008), pp. 446–459 D. Canright, L. Batina, A very compact ‘perfectly masked’ S-box for AES, in Lecture Notes in Computer Science (2008), pp. 446–459
go back to reference Z. Chen, Y. Zhou, Dual-rail random switching logic: a countermeasure to reduce side channel leakage, in Cryptographic Hardware and Embedded Systems (CHES) (2006), pp. 242–254 Z. Chen, Y. Zhou, Dual-rail random switching logic: a countermeasure to reduce side channel leakage, in Cryptographic Hardware and Embedded Systems (CHES) (2006), pp. 242–254
go back to reference B.D. Choi, T.W. Kim, D.K. Kim, Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process. IET J. Mag. 50(12), 876–877 (2014) B.D. Choi, T.W. Kim, D.K. Kim, Zero bit error rate ID generation circuit using via formation probability in 0.18 μm CMOS process. IET J. Mag. 50(12), 876–877 (2014)
go back to reference Y. Dodis, R. Ostrovsky, L. Reyzin, A. Smith, Fuzzy extractors: how to generate strong keys from biometrics and other noisy data. SIAM J. Comput. 38(1), 97–139 (2008)CrossRefMATH Y. Dodis, R. Ostrovsky, L. Reyzin, A. Smith, Fuzzy extractors: how to generate strong keys from biometrics and other noisy data. SIAM J. Comput. 38(1), 97–139 (2008)CrossRefMATH
go back to reference S. Eiroa, J. Castro, M. Martínez-Rodríguez, E. Tena, P. Brox, I. Baturone, Reducing bit flipping problems in SRAM physical unclonable functions for chip identification, in IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (2012), pp. 392–395 S. Eiroa, J. Castro, M. Martínez-Rodríguez, E. Tena, P. Brox, I. Baturone, Reducing bit flipping problems in SRAM physical unclonable functions for chip identification, in IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (2012), pp. 392–395
go back to reference D. Ganta, V. Vivekraja, K. Priya, L. Nazhandali, A highly stable leakage-based silicon physical unclonable functions, in International Conference on VLSI Design (2011), pp. 135–140 D. Ganta, V. Vivekraja, K. Priya, L. Nazhandali, A highly stable leakage-based silicon physical unclonable functions, in International Conference on VLSI Design (2011), pp. 135–140
go back to reference B. Gassend, D. Clarke, M. van Dijk, S. Devadas, Silicon physical random functions, in ACM Conference on Computer and Communications Security (CCS) (2002), p. 148 B. Gassend, D. Clarke, M. van Dijk, S. Devadas, Silicon physical random functions, in ACM Conference on Computer and Communications Security (CCS) (2002), p. 148
go back to reference J. Giorgetti, G. Scotti, A. Simonetti, A. Trifiletti, Analysis of data dependence of leakage current in CMOS cryptographic hardware, in Great Lakes Symposium on VLSI (GLSVLSI) (2007), pp. 78–83 J. Giorgetti, G. Scotti, A. Simonetti, A. Trifiletti, Analysis of data dependence of leakage current in CMOS cryptographic hardware, in Great Lakes Symposium on VLSI (GLSVLSI) (2007), pp. 78–83
go back to reference J. Guajardo, S.S. Kumar, G. Schrijen, P. Tuyls, FPGA intrinsic PUFs and their use for IP protection, in Lecture Notes in Computer Science, ed. by P. Paillier, I. Verbauwhede (Springer, Heidelberg, 2007), pp. 63–80 J. Guajardo, S.S. Kumar, G. Schrijen, P. Tuyls, FPGA intrinsic PUFs and their use for IP protection, in Lecture Notes in Computer Science, ed. by P. Paillier, I. Verbauwhede (Springer, Heidelberg, 2007), pp. 63–80
go back to reference R. Helinski, D. Acharyya, J. Plusquellic, A physical unclonable function defined using power distribution system equivalent resistance variations, in ACM/IEEE Design Automation Conference (2009), pp. 676–681 R. Helinski, D. Acharyya, J. Plusquellic, A physical unclonable function defined using power distribution system equivalent resistance variations, in ACM/IEEE Design Automation Conference (2009), pp. 676–681
go back to reference D.E. Holcomb, W.P. Burleson, K. Fu, Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)MathSciNetCrossRef D.E. Holcomb, W.P. Burleson, K. Fu, Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)MathSciNetCrossRef
go back to reference Intrinsic-ID, SRAM PUF: the secure silicon fingerprint, in White Paper (2016) Intrinsic-ID, SRAM PUF: the secure silicon fingerprint, in White Paper (2016)
go back to reference B. Karpinskyy, Y. Lee, Y. Choi, Y. Kim, M. Noh, S. Lee, Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45 nm smart-card chips, in IEEE International Solid-State Circuits Conference (ISSC) (2016), pp. 158–160 B. Karpinskyy, Y. Lee, Y. Choi, Y. Kim, M. Noh, S. Lee, Physically unclonable function for secure key generation with a key error rate of 2E-38 in 45 nm smart-card chips, in IEEE International Solid-State Circuits Conference (ISSC) (2016), pp. 158–160
go back to reference P. Kocher, J. Ja, B. Jun, Differential power analysis. Lect. Notes Comput. Sci. 1666, 388–397 (1999)CrossRefMATH P. Kocher, J. Ja, B. Jun, Differential power analysis. Lect. Notes Comput. Sci. 1666, 388–397 (1999)CrossRefMATH
go back to reference O. Kömmerling, M.G. Kuhn, Design principles for tamper-resistant smartcard processors, in USENIX Workshop on Smartcard Technology (1999), pp. 9–20 O. Kömmerling, M.G. Kuhn, Design principles for tamper-resistant smartcard processors, in USENIX Workshop on Smartcard Technology (1999), pp. 9–20
go back to reference S.S. Kumar, J. Guajardo, R. Maes, G. Schrijen, P. Tuyls, The butterfly PUF protecting IP on every FPGA, in IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) (2008), no. 71369, pp. 67–70 S.S. Kumar, J. Guajardo, R. Maes, G. Schrijen, P. Tuyls, The butterfly PUF protecting IP on every FPGA, in IEEE International Workshop on Hardware-Oriented Security and Trust (HOST) (2008), no. 71369, pp. 67–70
go back to reference J.W. Lee, B. Gassend, G.E. Suh, M. van Dijk, S. Devadas, A technique to build a secret key in integrated circuits for identification and authentication applications, in Symposium on VLSI Circuits (2004), pp. 176–179 J.W. Lee, B. Gassend, G.E. Suh, M. van Dijk, S. Devadas, A technique to build a secret key in integrated circuits for identification and authentication applications, in Symposium on VLSI Circuits (2004), pp. 176–179
go back to reference J. Li, M. Seok, A 3.07 μm^2/bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80 °C and 0.6 to 1.2 V in a 65 nm CMOS, in IEEE Symposium on VLSI Circuits, Digest of Technical Papers (2015), pp. 250–251 J. Li, M. Seok, A 3.07 μm^2/bitcell physically unclonable function with 3.5% and 1% bit-instability across 0 to 80 °C and 0.6 to 1.2 V in a 65 nm CMOS, in IEEE Symposium on VLSI Circuits, Digest of Technical Papers (2015), pp. 250–251
go back to reference D. Lim, J.W. Lee, B. Gassend, G.E. Suh, M. Van Dijk, S. Devadas, Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(10), 1200–1205 (2005)CrossRef D. Lim, J.W. Lee, B. Gassend, G.E. Suh, M. Van Dijk, S. Devadas, Extracting secret keys from integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 13(10), 1200–1205 (2005)CrossRef
go back to reference N. Liu, S. Hanson, D. Sylvester, D. Blaauw, OxID: on-chip one-time random ID generation using oxide breakdown, in Symposium on VLSI Circuits (2010), pp. 231–232 N. Liu, S. Hanson, D. Sylvester, D. Blaauw, OxID: on-chip one-time random ID generation using oxide breakdown, in Symposium on VLSI Circuits (2010), pp. 231–232
go back to reference K. Lofstrom, W.R. Daasch, D. Taylor, IC identification circuit using device mismatch. IEEE Int. Solid-State Circuits Conf. 46(8), 1999–2000 (2000) K. Lofstrom, W.R. Daasch, D. Taylor, IC identification circuit using device mismatch. IEEE Int. Solid-State Circuits Conf. 46(8), 1999–2000 (2000)
go back to reference R. Maes, Physically Unclonable Functions: Construction, Properties and Applications (Springer, London, 2013)CrossRefMATH R. Maes, Physically Unclonable Functions: Construction, Properties and Applications (Springer, London, 2013)CrossRefMATH
go back to reference R. Maes, Physically unclonable functions : constructions, properties and applications. Katholieke Universiteit Leuven (2012) R. Maes, Physically unclonable functions : constructions, properties and applications. Katholieke Universiteit Leuven (2012)
go back to reference R. Maes, P. Tuyls, I. Verbauwhede, Intrinsic PUFs from flip-flops on reconfigurable devices, in Workshop on Information and System Security (2008), no. 71369, pp. 1–17 R. Maes, P. Tuyls, I. Verbauwhede, Intrinsic PUFs from flip-flops on reconfigurable devices, in Workshop on Information and System Security (2008), no. 71369, pp. 1–17
go back to reference R. Maes, P. Tuyls, I. Verbauwhede, A soft decision helper data algorithm for SRAM PUFs, in IEEE International Symposium on Information Theory (2009), pp. 2101–2105 R. Maes, P. Tuyls, I. Verbauwhede, A soft decision helper data algorithm for SRAM PUFs, in IEEE International Symposium on Information Theory (2009), pp. 2101–2105
go back to reference R. Maes, P. Tuyls, I. Verbauwhede, “Low-overhead implementation of a soft decision helper data algorithm for SRAM PUFs, in Cryptographic Hardware and Embedded Systems (CHES) (2009), pp. 1–15 R. Maes, P. Tuyls, I. Verbauwhede, “Low-overhead implementation of a soft decision helper data algorithm for SRAM PUFs, in Cryptographic Hardware and Embedded Systems (CHES) (2009), pp. 1–15
go back to reference R. Maes, V. Rozic, I. Verbauwhede, P. Koeberl, E. van der Sluis V. can der Leest, Experimental evaluation of physically unclonable functions in 65 nm CMOS, in European Solid State Circuit Conference (ESSCIRC) (2012), pp. 486–489 R. Maes, V. Rozic, I. Verbauwhede, P. Koeberl, E. van der Sluis V. can der Leest, Experimental evaluation of physically unclonable functions in 65 nm CMOS, in European Solid State Circuit Conference (ESSCIRC) (2012), pp. 486–489
go back to reference S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards (Springer, New York, 2007)MATH S. Mangard, E. Oswald, T. Popp, Power Analysis Attacks: Revealing the Secrets of Smart Cards (Springer, New York, 2007)MATH
go back to reference S.K. Mathew, S.K. Satpathy, M.A. Anders, H. Kaul, S.K. Hsu, A. Agarwal, G.K. Chen, R.J. Parker, R.K. Krishnamurthy, V. De, A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22 nm CMOS. Digest Tech. Pap. - IEEE Int. Solid-State Circuits Conf. 2(c), 278–280 (2014) S.K. Mathew, S.K. Satpathy, M.A. Anders, H. Kaul, S.K. Hsu, A. Agarwal, G.K. Chen, R.J. Parker, R.K. Krishnamurthy, V. De, A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22 nm CMOS. Digest Tech. Pap. - IEEE Int. Solid-State Circuits Conf. 2(c), 278–280 (2014)
go back to reference S. Mathew, S. Satpathy, V. Suresh, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen, R. Krishnamurthy, V. De, A 4fJ/bit delay-hardened Physically unclonable function circuit with selective bit destabilization in 14 nm trti-gate CMOS, in Symposium on VLSI Circuits (2016), pp. 248–249 S. Mathew, S. Satpathy, V. Suresh, M. Anders, H. Kaul, A. Agarwal, S. Hsu, G. Chen, R. Krishnamurthy, V. De, A 4fJ/bit delay-hardened Physically unclonable function circuit with selective bit destabilization in 14 nm trti-gate CMOS, in Symposium on VLSI Circuits (2016), pp. 248–249
go back to reference D. Merli, F. Stumpf, G. Sigl, Protecting PUF error correction by codeword masking (2013), pp. 1–16 D. Merli, F. Stumpf, G. Sigl, Protecting PUF error correction by codeword masking (2013), pp. 1–16
go back to reference C. Monteiro, Y. Takahashi, T. Sekine, “Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart cards, in International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) (2011), pp. 1–5 C. Monteiro, Y. Takahashi, T. Sekine, “Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart cards, in International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) (2011), pp. 1–5
go back to reference D. Nedospasov, J.P. Seifert, C. Helfmeier, C. Boit, Invasive PUF analysis, in Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC) (2013), pp. 30–38 D. Nedospasov, J.P. Seifert, C. Helfmeier, C. Boit, Invasive PUF analysis, in Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC) (2013), pp. 30–38
go back to reference R. Pappu, B. Recht, J. Taylor, N. Gershenfeld, Physical one-way functions. Science 297, 2026–2030 (2002)CrossRef R. Pappu, B. Recht, J. Taylor, N. Gershenfeld, Physical one-way functions. Science 297, 2026–2030 (2002)CrossRef
go back to reference Z.S. Paral, S. Devadas, Reliable and efficient PUF-based key generation using pattern matching, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2011), no. 978, pp. 128–133 Z.S. Paral, S. Devadas, Reliable and efficient PUF-based key generation using pattern matching, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2011), no. 978, pp. 128–133
go back to reference T. Popp, S. Mangard, Masked dual-rail pre-charge logic: DPA-resistance without routing constraints, in Cryptographic Hardware and Embedded Systems (CHES) (2005), pp. 172–186 T. Popp, S. Mangard, Masked dual-rail pre-charge logic: DPA-resistance without routing constraints, in Cryptographic Hardware and Embedded Systems (CHES) (2005), pp. 172–186
go back to reference D. Puntin, S. Stanzione, G. Iannaccone, CMOS unclonable system for secure authentication based on device variability, in European Solid State Circuit Conference (ESSCIRC) (2008), pp. 130–133 D. Puntin, S. Stanzione, G. Iannaccone, CMOS unclonable system for secure authentication based on device variability, in European Solid State Circuit Conference (ESSCIRC) (2008), pp. 130–133
go back to reference M.T. Rahman, D. Forte, J. Fahrny, M. Tehranipoor, ARO-PUF: an aging-resistant ring oscillator PUF design, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2014), pp. 1–6 M.T. Rahman, D. Forte, J. Fahrny, M. Tehranipoor, ARO-PUF: an aging-resistant ring oscillator PUF design, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2014), pp. 1–6
go back to reference S. Rosenblatt, D. Fainstein, A. Cestero, J. Safran, N. Robson, T. Kirihata, S.S. Iyer, Field tolerant dynamic intrinsic chip ID using 32 nm high-K/metal gate SOI embedded DRAM. IEEE J. Solid State Circuits 48(4), 940–947 (2013)CrossRef S. Rosenblatt, D. Fainstein, A. Cestero, J. Safran, N. Robson, T. Kirihata, S.S. Iyer, Field tolerant dynamic intrinsic chip ID using 32 nm high-K/metal gate SOI embedded DRAM. IEEE J. Solid State Circuits 48(4), 940–947 (2013)CrossRef
go back to reference D. Roy, J.H. Klootwijk, N.A.M. Verhaegh, H.H.A.J. Roosen, R.A.M. Wolters, Comb capacitor structures for on-chip physical uncloneable function. IEEE Trans. Semicond. Manuf. 22(1), 96–102 (2009)CrossRef D. Roy, J.H. Klootwijk, N.A.M. Verhaegh, H.H.A.J. Roosen, R.A.M. Wolters, Comb capacitor structures for on-chip physical uncloneable function. IEEE Trans. Semicond. Manuf. 22(1), 96–102 (2009)CrossRef
go back to reference U. Rührmair, F. Sehnke, J. Sölter, G. Dror, S. Devadas, J. ürgen Schmidhuber, Modeling attacks on physical unclonable functions, in Proceedings of ACM Conference on Computer and Communications Security (2010), pp. 237–249 U. Rührmair, F. Sehnke, J. Sölter, G. Dror, S. Devadas, J. ürgen Schmidhuber, Modeling attacks on physical unclonable functions, in Proceedings of ACM Conference on Computer and Communications Security (2010), pp. 237–249
go back to reference U. Rührmair, J. Sölter, F. Sehnke, X. Xu, A. Mahmoud, V. Stoyanova, G. Dror, J. Schmidhuber, W. Burleson, S. Devadas, PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8(11), 1876–1891 (2013)CrossRef U. Rührmair, J. Sölter, F. Sehnke, X. Xu, A. Mahmoud, V. Stoyanova, G. Dror, J. Schmidhuber, W. Burleson, S. Devadas, PUF modeling attacks on simulated and silicon data. IEEE Trans. Inf. Forensics Secur. 8(11), 1876–1891 (2013)CrossRef
go back to reference A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert, J. Dray, S. Vo, A statistical test suite for random and pseudorandom number generators for cryptographic applications. Natl. Inst. Stand. Technol. 800–22(Rev 1a), 131 (2010) A. Rukhin, J. Soto, J. Nechvatal, M. Smid, E. Barker, S. Leigh, M. Levenson, M. Vangel, D. Banks, A. Heckert, J. Dray, S. Vo, A statistical test suite for random and pseudorandom number generators for cryptographic applications. Natl. Inst. Stand. Technol. 800–22(Rev 1a), 131 (2010)
go back to reference A.-R. Sadeghi, D. Naccache (eds.), Towards Hardware-Intrinsic Security: Foundations and Practice (Springer, Berlin, 2010)MATH A.-R. Sadeghi, D. Naccache (eds.), Towards Hardware-Intrinsic Security: Foundations and Practice (Springer, Berlin, 2010)MATH
go back to reference D. Samyde, S. Skorobogatov, R. Anderson, J.-J. Quisquater, On a new way to read data from memory, in International IEEE Security in Storage Workshop (2002), pp. 65–69 D. Samyde, S. Skorobogatov, R. Anderson, J.-J. Quisquater, On a new way to read data from memory, in International IEEE Security in Storage Workshop (2002), pp. 65–69
go back to reference S. Satpathy, S. Mathew, J. Li, P. Koeberl, M. Anders, H. Kaul, G. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy, 13fJ/bit probing-resilient 250 K PUF array with soft dark-bit masking for 1.94% bit-error in 22 nm tri-gate CMOS,” in European Solid State Circuit Conference (ESSCIRC) (2014), pp. 239–242 S. Satpathy, S. Mathew, J. Li, P. Koeberl, M. Anders, H. Kaul, G. Chen, A. Agarwal, S. Hsu, R. Krishnamurthy, 13fJ/bit probing-resilient 250 K PUF array with soft dark-bit masking for 1.94% bit-error in 22 nm tri-gate CMOS,” in European Solid State Circuit Conference (ESSCIRC) (2014), pp. 239–242
go back to reference P. Schaumont, K. Tiri, Masking and dual-rail logic don’t add up, in Cryptographic Hardware and Embedded Systems (CHES) (2007), pp. 95–106 P. Schaumont, K. Tiri, Masking and dual-rail logic don’t add up, in Cryptographic Hardware and Embedded Systems (CHES) (2007), pp. 95–106
go back to reference G.-J. Schrijen, V. Van Der Leest, Comparative analysis of SRAM memories used as PUF primitives, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2012), pp. 1319–1324 G.-J. Schrijen, V. Van Der Leest, Comparative analysis of SRAM memories used as PUF primitives, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2012), pp. 1319–1324
go back to reference G. Selimis, M. Konijnenburg, M. Ashouei, J. Huisken, H. De Groot, V. Van Der Leest, G.J. Schrijen, M. Van Hulst, P. Tuyls, “Evaluation of 90nm 6T-SRAM as physical unclonable function for secure key generation in wireless sensor nodes, Proceedings of IEEE International Symposium on Circuits Systems (2011), pp. 567–570 G. Selimis, M. Konijnenburg, M. Ashouei, J. Huisken, H. De Groot, V. Van Der Leest, G.J. Schrijen, M. Van Hulst, P. Tuyls, “Evaluation of 90nm 6T-SRAM as physical unclonable function for secure key generation in wireless sensor nodes, Proceedings of IEEE International Symposium on Circuits Systems (2011), pp. 567–570
go back to reference M. Shiozaki, T. Kubota, T. Nakai, A. Takeuchi, T. Nishimura, T. Fujino, Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. in IEEE International Symposium on Circuits and Systems (ISCAS) (2015), pp. 1462–1465 M. Shiozaki, T. Kubota, T. Nakai, A. Takeuchi, T. Nishimura, T. Fujino, Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. in IEEE International Symposium on Circuits and Systems (ISCAS) (2015), pp. 1462–1465
go back to reference P. Simons, E. Van Der Sluis, V. Van Der Leest, Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2012), pp. 7–12 P. Simons, E. Van Der Sluis, V. Van Der Leest, Buskeeper PUFs, a promising alternative to D Flip-Flop PUFs, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2012), pp. 7–12
go back to reference S.W. Smith, S. Weingart, Building a high-performance, programmable secure coprocessor. Comput. Networks 31(8), 831–860 (1999)CrossRef S.W. Smith, S. Weingart, Building a high-performance, programmable secure coprocessor. Comput. Networks 31(8), 831–860 (1999)CrossRef
go back to reference S. Stanzione, G. Iannaccone, Silicon physical unclonable function resistant to a 10^25-trial brute force attack in 90 nm CMOS, in Symposium on VLSI Circuits (2009), pp. 116–117 S. Stanzione, G. Iannaccone, Silicon physical unclonable function resistant to a 10^25-trial brute force attack in 90 nm CMOS, in Symposium on VLSI Circuits (2009), pp. 116–117
go back to reference Y. Su, J. Holleman B. Otis, A 1.6pJ/bit 96% stable chip-ID generating circuit using process variations, in Digest of Technical Papers - IEEE International Solid-State Circuits Conference (ISSCC) (2007), pp. 406–408 Y. Su, J. Holleman B. Otis, A 1.6pJ/bit 96% stable chip-ID generating circuit using process variations, in Digest of Technical Papers - IEEE International Solid-State Circuits Conference (ISSCC) (2007), pp. 406–408
go back to reference G.E. Suh, S. Devadas, Physical unclonable functions for device authentication and secret key generation, in ACM/IEEE Design Automation Conference (2007), pp. 9–14 G.E. Suh, S. Devadas, Physical unclonable functions for device authentication and secret key generation, in ACM/IEEE Design Automation Conference (2007), pp. 9–14
go back to reference G.E. Suh, C.W. O’Donnell, S. Devadas, Aegis: a single-chip secure processor. IEEE Des. Test Comput. 24(6), 570–580 (2007b)CrossRef G.E. Suh, C.W. O’Donnell, S. Devadas, Aegis: a single-chip secure processor. IEEE Des. Test Comput. 24(6), 570–580 (2007b)CrossRef
go back to reference D. Suzuki, K. Shimizu, The glitch PUF: a new delay-PUF architecture exploiting glitch shapes, in Workshop on Cryptographic Hardware and Embedded Systems (CHES) (2010), pp. 366–382 D. Suzuki, K. Shimizu, The glitch PUF: a new delay-PUF architecture exploiting glitch shapes, in Workshop on Cryptographic Hardware and Embedded Systems (CHES) (2010), pp. 366–382
go back to reference K. Tiri, M. Akmal, I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, in European Solid-State Circuits Conference (ESSCIRC) (2002), pp. 403–406 K. Tiri, M. Akmal, I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, in European Solid-State Circuits Conference (ESSCIRC) (2002), pp. 403–406
go back to reference K. Tiri, I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2004), pp. 246–251 K. Tiri, I. Verbauwhede, A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (2004), pp. 246–251
go back to reference P. Tuyls, G.-J. Schrijen, B. Škorić, J. van Geloven, N. Verhaegh, R. Wolters, Read-proof hardware from protective coatings, in Cryptographic Hardware and Embedded Systems (CHES) (2006), pp. 369–383 P. Tuyls, G.-J. Schrijen, B. Škorić, J. van Geloven, N. Verhaegh, R. Wolters, Read-proof hardware from protective coatings, in Cryptographic Hardware and Embedded Systems (CHES) (2006), pp. 369–383
go back to reference M. Wan, Z. He, S. Han, K. Dai, X. Zou, An invasive-attack-resistant PUF based on switched-capacitor circuit. IEEE Trans. Circuits Syst. I 62(8), 2024–2034 (2015)MathSciNetCrossRef M. Wan, Z. He, S. Han, K. Dai, X. Zou, An invasive-attack-resistant PUF based on switched-capacitor circuit. IEEE Trans. Circuits Syst. I 62(8), 2024–2034 (2015)MathSciNetCrossRef
go back to reference T. Xu, J.B. Wendt, M. Potkonjak, Matched digital PUFs for low power security in implantable medical devices, 2014 I.E. International Conference on Healthcare Informatics (2014), pp. 33–38 T. Xu, J.B. Wendt, M. Potkonjak, Matched digital PUFs for low power security in implantable medical devices, 2014 I.E. International Conference on Healthcare Informatics (2014), pp. 33–38
go back to reference K. Yang, Q. Dong, D. Blaauw, D. Sylvester, A physically unclonable function with BER < 10^-8 for robust chip authentication using oscillator collapse in 40 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2015), pp. 254–256 K. Yang, Q. Dong, D. Blaauw, D. Sylvester, A physically unclonable function with BER < 10^-8 for robust chip authentication using oscillator collapse in 40 nm CMOS, in IEEE International Solid-State Circuits Conference (ISSCC) (2015), pp. 254–256
go back to reference M.M. Yu, S. Devadas, Secure and robust error correction for physical unclonable functions. IEEE Des. Test Comput. 27(1), 48–65 (2010)CrossRef M.M. Yu, S. Devadas, Secure and robust error correction for physical unclonable functions. IEEE Des. Test Comput. 27(1), 48–65 (2010)CrossRef
go back to reference M.M. Yu, D.M. Raihi, R. Sowell, S. Devadas, Lightweight and secure PUF key storage using limits of machine learning, in Workshop on Cryptographic Hardware and Embedded Systems (2011), pp. 358–373 M.M. Yu, D.M. Raihi, R. Sowell, S. Devadas, Lightweight and secure PUF key storage using limits of machine learning, in Workshop on Cryptographic Hardware and Embedded Systems (2011), pp. 358–373
go back to reference M.M. Yu, R. Sowell, A. Singh, D.M. Raihi, S. Devadas, Performance metrics and empirical results of a PUF cryptographic key generation ASIC, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2012), pp. 108–115 M.M. Yu, R. Sowell, A. Singh, D.M. Raihi, S. Devadas, Performance metrics and empirical results of a PUF cryptographic key generation ASIC, in IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) (2012), pp. 108–115
go back to reference W. Zhao, Y. Ha, M. Alioto, Novel self-body-biasing and statistical design for near-threshold circuits with ultra energy-efficient AES as case study. IEEE Trans. VLSI Systems 23(8), 1390–1401 (2015)CrossRef W. Zhao, Y. Ha, M. Alioto, Novel self-body-biasing and statistical design for near-threshold circuits with ultra energy-efficient AES as case study. IEEE Trans. VLSI Systems 23(8), 1390–1401 (2015)CrossRef
Metadata
Title
Security Down to the Hardware Level
Authors
Anastacia Alvarez
Massimo Alioto
Copyright Year
2017
DOI
https://doi.org/10.1007/978-3-319-51482-6_8