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Published in: Microsystem Technologies 2/2008

01-02-2008 | Technical Paper

Shrinkage ratio of PDMS and its alignment method for the wafer level process

Authors: Seok Woo Lee, Seung S. Lee

Published in: Microsystem Technologies | Issue 2/2008

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Abstract

In the research area known as Lab-on-a-Chip, poly-dimethylsiloane (PDMS) is a popular material whose fabrication method is the replication of patterns by curing on a mold. Shrinkage of PDMS occurs when it is cured; this is a problem related to the alignment between the PDMS layer and the rigid substrate during the wafer-level processing. In this paper, the 2D shrinkage ratio of PDMS is measured experimentally for various curing conditions including the temperature, thickness, and mixing ratio of the curing agent and dilutant. In order to measure this, scale marks were patterned onto a 4 in. wafer and replicated onto a PDMS substrate. When the patterned Si wafer and PDMS substrate were aligned, the difference of each scale mark was observed. A cross-shaped groove was patterned with a scale mark as a align key for the easy alignment of substrates. For a general recipe, the measured shrinkage ratios of PDMS were 1.06, 1.52 and 1.94% for curing temperature of 65, 80 and 100°C, respectively. Considering the shrinkage ratio of PDMS, the design offset applied in a photomask is 1.07, 1.54 and 1.98% for curing temperature of 65, 80 and 100°C, respectively.

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Literature
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Metadata
Title
Shrinkage ratio of PDMS and its alignment method for the wafer level process
Authors
Seok Woo Lee
Seung S. Lee
Publication date
01-02-2008
Publisher
Springer-Verlag
Published in
Microsystem Technologies / Issue 2/2008
Print ISSN: 0946-7076
Electronic ISSN: 1432-1858
DOI
https://doi.org/10.1007/s00542-007-0417-y

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