1. High-k Dielectric for Nanoscale MOS Devices

The continuous shrinking of device dimensions in order to follow Moore’s Law makes SiO₂ almost meets its physical limit in thickness, hence gate insulators with higher dielectric constant (high-k) to maintain sufficient capacitance are necessary for MOS devices. Promising candidates such as Hf-based high-k material have already been applied commercially, and La₂O₃, Ta₂O₅, ZrO₂, etc. have been paid much attention in recent years. On the other hand, replacing Si with Ge or III-V compound semiconductors including GaAs, InGaAs, GaN, etc. to further increase carrier mobility is another trend to meet the requirements of future CMOS technology. However, unlike the stable SiO₂ and the excellent SiO₂/Si interface, challenges including (1) thermodynamic and kinetic stability, (2) high-k/substrate and high-k/metal gate interface engineering, (3) mobility degradation and threshold voltage shift in high-k dielectrics on Si, Ge or III-V compounds still remain. Therefore, based on the mechanism and current progress of high-k materials, a review of the current status and challenges in high-k dielectrics applied in MOS devices is made in this chapter. Section 1.1 gives a brief introduction of the background of this area. Section 1.2 introduces the basic mechanism and properties of high-k materials. Section 1.3 compares different high-k dielectric deposition methods. While Sects. 1.4 and 1.5 focus on the applications of promising candidates of high-k dielectrics (Hf-, rare earth-, and perovskite-based) in varieties of MOS devices.