Skip to main content
Disciplines
Automotive Business IT + Informatics Construction + Real Estate Electrical Engineering + Electronics Energy + Sustainability Insurance + Risk Finance + Banking Management + Leadership Marketing + Sales Mechanical Engineering + Materials
Events
DE
EN
Books
Journals
Topic Page
Marketing
Start single access now
Access for companies
EXTENDED SEARCH
Log in
Top
Journal of Computational Electronics
Published in: Journal of Computational Electronics 2/2016

21-03-2016

Modeling and simulation of cylindrical surrounding double-gate (CSDG) MOSFET with vacuum gate dielectric for improved hot-carrier reliability and RF performance

Authors: Jay Hind Kumar Verma, Subhasis Haldar, R. S. Gupta, Mridula Gupta

Published in: Journal of Computational Electronics | Issue 2/2016

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

We present modeling and simulation of a cylindrical surrounding double-gate (CSDG) metal–oxide–semiconductor field-effect transistor (MOSFET) with vacuum gate dielectric instead of silicon dioxide, revealing some improvement in hot-carrier reliability. The CSDG MOSFET incorporates an extra inner control gate compared with the cylindrical surrounding gate (CSG) MOSFET, resulting in improved drain current in the channel. The radiofrequency (RF) performance of the CSDG MOSFET is obtained and compared for different dielectrics such as vacuum, silicon dioxide, and high-k material. The RF performance of the CSDG MOSFETs is evaluated on the basis of transconductance, capacitance, cutoff frequency, and drain current. Also, the surface potential and electric field are evaluated analytically at higher drain bias. It is shown that, with decreasing gate dielectric constant, the threshold voltage decreases while hot-carrier parameters such as the electron temperature are reduced at the drain side.
previous article Large-signal characterization of millimeter-wave IMPATTs: effect of reduced impact ionization rate of charge carriers due to carrier-carrier interactions
next article Model for threshold voltage instability in top-gated nanocrystalline silicon thin film transistor

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

inform now

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

inform now
Literature
1.
Taur, Y.: An analytical solution to a double-gate MOSFET with undoped body. IEEE Electron Device Lett. 21(5), 245–247 (2000)CrossRef
2.
Han, J.W., Kim, C.J., Choi, Y.K.: Universal Potential Model in Tied and Separated Double-Gate MOSFETs with Consideration of Symmetric and Asymmetric Structure. IEEE Trans. Electron Devices 55(6), 1472–1479 (2008)CrossRef
3.
Doyle, B.S., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., Linton, T., Murthy, A., Rios, R., Chau, R.: High Performance Fully-Depleted Tri-Gate CMOS Transistors. IEEE Electron Device Lett. 24(4), 263–265 (2003)CrossRef
4.
Colinge, J.P.: Multiple-gate SOI MOSFETs. Solid-State Electron. 48, 897–905 (2004)CrossRef
5.
Lee, H., Yu, L. E., Ryu, S. W., Han, J. W., Jeon, K., Jang, D.Y., Choi, Y. K.: Sub-5nm all-around gate FinFET for ultimate scaling. IEEE Symposium on VLSI Technology, Digest of Technical Papers 58-59 (2006)
6.
Li, C., Zhuang, Y., Han, R.: Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension. Microelectron. Eng. 42, 341–346 (2011)CrossRef
7.
Kranti, A., Haldar, S., Gupta, R.S.: An accurate 2D analytical model for short channel thin film fully depleted cylindrical/surrounding gate (CGT/SGT) MOSFET. Microelectron. J. 32, 305–313 (2001)CrossRef
8.
Fahad, H.M., Smith, C.E., Rojas, J.P., Hussain, M.M.: Silicon Nano-tube Field Effect Transistor with Core Shell Gate Stacks for Enhanced High-Performance Operation and Area Scaling Benefits. Nano Lett. 11, 4393–4399 (2011)CrossRef
9.
Ge, L.J., Fossum, G., Gamiz, F.: Mobility Enhancement via Volume Inversion in Double-Gate MOSFETs. IEEE international SOI conference, USA. (2003)
10.
Srivastava, V.M., Yadav, K.S., Singh, G.: Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF Switch. Microelectron. J. 42, 1124–1135 (2011)CrossRef
11.
Chen, Y., Kang, W.: Experimental study and modeling of double-surrounding gate and cylindrical silicon-on-nothing MOSFETs. Microelectron. Eng. 97, 138–143 (2012)CrossRef
12.
Tekleab, D.: Device Performance of Silicon Nanotube Field Effect Transistor. IEEE Electron Device Lett. 35(5), 506–508 (2014)CrossRef
13.
Ernst, T., Cristoloveanu, S., Ouisse, T., Murase, K.: Ultimately thin double gate SOI MOSFETs. IEEE Trans. Electron Devices 50(3), 830–836 (2003)CrossRef
14.
Xia, Y., Kalihari, V., Frisbie, C.D.: Tetracene air-gap single-crystal field-effect transistors. App. Phy. Lett. 90, 162106 (2007)CrossRef
15.
Han, J.W., Ahn, J.H., Choi, Y.K.: Damage immune field effect transistors with vacuum gate dielectric. J. Vacuum Sc. Tech. B. 29, 011014 (2011)CrossRef
16.
Gautam, R., Saxena, M., Gupta, R.S., Gupta, M.: Gate All Around MOSFET with Vacuum Gate Dielectric for Improved Hot Carrier Reliability and RF Performance. IEEE Trans. Electron Devices 60, 1820–1827 (2013)CrossRef
17.
Han, J.W., Moon, D.I., Oh, J.S., Choi, Y.K., Meyyappan, M.: Vacuum gate dielectric gate-all-around nanowire for hot carrier injection and bias temperature instability free transistor. App. Phy. Lett. 104, 253506 (2014)CrossRef
18.
ATLAS: 3D Device Simulator. SILVACO International (2015)
19.
Singh, N., Agarwal, A., Bera, L.K., Liow, T.Y., Yang, R., Rustagi, S.C., Kwong, D.L.: High-performance fully depleted silicon nanowire (diameter_5 nm) gate all-around CMOS devices. IEEE Electron Device Lett. 27, 383–386 (2006)
20.
Kumar, J., Kedzierski, S., Laux, E.: Quantum-based simulation analysis of scaling in ultrathin body device structures. IEEE Trans. Electron Devices 52, 614–617 (2005)CrossRef
21.
Hamid, E.L., Hamdy, A., Iniguez, B., Guitart, J.R.: Analytical model of the threshold voltage and sub-threshold swing of undoped cylindrical gate-all-around based MOSFETs. IEEE Trans. Electron Devices 54, 572–579 (2007)CrossRef
22.
Ren, H., Hao, Y.: The influence of geometric structure on the hot carrier-effect immunity for deep-sub-micron grooved gate PMOSFET. Solid-State Electron. 46(5), 665–673 (2002)CrossRef
23.
Tam, S., Ko, P.K., Hu, C.: Lucky-electron model of channel hot electron injection in MOSFET’s. IEEE Trans. Electron Devices 31(9), 1116–1125 (1984)CrossRef
24.
Widiez, J., Poiroux, T., Vinet, M., Mouis, M., Deleonibus, S.: Experimental Comparison between Sub-0.1-Ultrathin SOI Single-and Double-Gate MOSFETs: Performance and Mobility. IEEE Trans. Nanotech 52, 643–648 (2006)CrossRef
25.
Iwai, H.: Roadmap for 22 nm and beyond. Microelectron. Eng. 86, 1520–1528 (2009)CrossRef
Metadata
Title
Modeling and simulation of cylindrical surrounding double-gate (CSDG) MOSFET with vacuum gate dielectric for improved hot-carrier reliability and RF performance
Authors
Jay Hind Kumar Verma
Subhasis Haldar
R. S. Gupta
Mridula Gupta
Publication date
21-03-2016
Publisher
Springer US
Published in
Journal of Computational Electronics / Issue 2/2016
Print ISSN: 1569-8025
Electronic ISSN: 1572-8137
DOI
https://doi.org/10.1007/s10825-016-0803-8

Other articles of this Issue 2/2016

Journal of Computational Electronics 2/2016 Go to the issue

OriginalPaper

Nested dissection solver for transport in 3D nano-electronic devices

OriginalPaper

A numerical study of forming voltage and switching polarity dependence on Ti top electrode thickness in Zr $$\mathrm{O}_2$$ O 2 RRAM

OriginalPaper

Two-dimensional analytical model of threshold voltage and drain current of a double-halo gate-stacked triple-material double-gate MOSFET

OriginalPaper

DFT studies of electronic structure and dielectric properties in layered perovskite $$\hbox {LaSrAlO}_{4}$$ LaSrAlO 4

OriginalPaper

Control of gold nano-domes to design an all-optical switch by simultaneously binary and continuous operated optimization

OriginalPaper

0.22 THz two-stage cascaded staggered double-vane traveling-wave tube