Skip to main content
Top
Published in: Journal of Electronic Testing 6/2016

26-10-2016

Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression

Authors: Harpreet Vohra, Amardeep Singh

Published in: Journal of Electronic Testing | Issue 6/2016

Log in

Activate our intelligent search to find suitable subject content or patents.

search-config
loading …

Abstract

Test data volume amount is increased multi-fold due to the need of quality assurance of various parts of the circuit design at deep submicron level. Huge memory is required to store this enormous test data which not only increases the cost of the ATE but also the test application time. This paper presents an optimal selective count compatible run length (OSCCPRL) encoding scheme for achieving maximum compression for reduction of the test cost. OSCCPRL is a hybrid technique that amalgamates the benefits of other two techniques: 10 Coded run length (10 C) and Selective CCPRL (SCCPRL) proposed here. These techniques work on improvement of the 9 C and CCPRL techniques. In OSCCPRL, entire data is segmented in blocks and further compressed using inter block and intra block level merging techniques. SCCPRL technique is used for encoding the compatible blocks while the 10C is used to do encoding at sub block (half block length) level. In case, if no compatibility is found at block/sub block level then the unique pattern is held as such in the encoded data along with the necessary categorization bits. The decompression architecture is described and it is shown how by just the addition of few states of FSM, better test data compression can be achieved as compared to previous schemes. The simulation results performed for various ISCAS benchmarks circuits prove that the proposed OSCCPRL technique provides an average compression efficiency of around 80 %.

Dont have a licence yet? Then find out more about our products and how to get one now:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Show more products
Literature
1.
go back to reference Bayraktaroglu I, Orailoglu A. (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In: Proceedings IEEE VLSI test symposium (VTS), pp 113–118. Bayraktaroglu I, Orailoglu A. (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. In: Proceedings IEEE VLSI test symposium (VTS), pp 113–118.
2.
go back to reference Chandra A, Chakrabarty K (2001) System-on-a-chip data compression and decompression architecture based on Golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368CrossRef Chandra A, Chakrabarty K (2001) System-on-a-chip data compression and decompression architecture based on Golomb codes. IEEE Trans Comput Aided Des Integr Circuits Syst 20(3):355–368CrossRef
3.
go back to reference Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Commun 52(8):1076–1088 Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Commun 52(8):1076–1088
4.
go back to reference Chandra A, Chakrabarty K (2003) A unified approach to reduce SoC test data volume, scan power and testing time. IEEE Trans Comput Aided Des Integr Circuits Syst 22(3):352–363CrossRef Chandra A, Chakrabarty K (2003) A unified approach to reduce SoC test data volume, scan power and testing time. IEEE Trans Comput Aided Des Integr Circuits Syst 22(3):352–363CrossRef
5.
go back to reference Chang CH, Lee LJ, Tseng WD, Lin RB (2012) 2n pattern run-length for test data compression. IEEE Trans Comput Aided Des Integr Circuits Syst 31(4):644–648CrossRef Chang CH, Lee LJ, Tseng WD, Lin RB (2012) 2n pattern run-length for test data compression. IEEE Trans Comput Aided Des Integr Circuits Syst 31(4):644–648CrossRef
6.
go back to reference El-Maleh AH (2008) Efficient test compression technique based on block merging. IET Comput Digit Tech 2(5):327–335CrossRef El-Maleh AH (2008) Efficient test compression technique based on block merging. IET Comput Digit Tech 2(5):327–335CrossRef
7.
go back to reference El-Maleh AH (2008) Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput Digit Tech 2(3):155–163CrossRef El-Maleh AH (2008) Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput Digit Tech 2(3):155–163CrossRef
8.
go back to reference Gonciari P.T., Al-Hashimi B.M., Nicolici N.(2002) Improving compression ratio, area overhead, and test application time for system on-a-chip test data compression/decompression. In: Proceedings IEEE design automation and test in Europe conference and exhibition (DATE), pp 604–611 Gonciari P.T., Al-Hashimi B.M., Nicolici N.(2002) Improving compression ratio, area overhead, and test application time for system on-a-chip test data compression/decompression. In: Proceedings IEEE design automation and test in Europe conference and exhibition (DATE), pp 604–611
9.
go back to reference Gonciari PT, Hashimi BA, Nicolici N (2003) Variable-length input huffman coding for system-on-a-chip test. IEEE Trans Computer-Aided Design 22:783–796CrossRef Gonciari PT, Hashimi BA, Nicolici N (2003) Variable-length input huffman coding for system-on-a-chip test. IEEE Trans Computer-Aided Design 22:783–796CrossRef
10.
go back to reference Haiying Y, Kun G, Xun S, Zijian J (2016) Power Efficient test data compression method for SoC using alternating statistical Run-length coding. J Electron Test 32:59–68CrossRef Haiying Y, Kun G, Xun S, Zijian J (2016) Power Efficient test data compression method for SoC using alternating statistical Run-length coding. J Electron Test 32:59–68CrossRef
11.
go back to reference Jas A, Ghosh DJ, Ng M-E, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Comput Aided Des 22:797–806CrossRef Jas A, Ghosh DJ, Ng M-E, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Comput Aided Des 22:797–806CrossRef
12.
go back to reference Krishna C, Touba N.A. (2002) Reducing test data volume using LFSR reseeding with seed compression. In: Proceedings IEEE international test conference (ITC), pp 321–330. Krishna C, Touba N.A. (2002) Reducing test data volume using LFSR reseeding with seed compression. In: Proceedings IEEE international test conference (ITC), pp 321–330.
13.
go back to reference Lee H-H S, Chakrabarty K (2009) Test challenges for 3D integrated circuits. IEEE Des Test Comput 26(5):26–35CrossRef Lee H-H S, Chakrabarty K (2009) Test challenges for 3D integrated circuits. IEEE Des Test Comput 26(5):26–35CrossRef
14.
go back to reference Lee L-J, Tseng W-D, Lin R-B (2011) An internal pattern run-length methodology for slice encoding. ETRI J 33(3):374–381CrossRef Lee L-J, Tseng W-D, Lin R-B (2011) An internal pattern run-length methodology for slice encoding. ETRI J 33(3):374–381CrossRef
15.
go back to reference Li L, Chakrabarty K (2003) Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans Des Autom Electron Syst 8(4):470–490CrossRef Li L, Chakrabarty K (2003) Test data compression using dictionaries with selective entries and fixed-length indices. ACM Trans Des Autom Electron Syst 8(4):470–490CrossRef
16.
go back to reference Mehta US, Dasgupta KS, Devashrayee NM (2010) Modified selective Huffman coding for optimization of test data compression, test application time and area overhead. J Electron Test 26(6):679–688CrossRef Mehta US, Dasgupta KS, Devashrayee NM (2010) Modified selective Huffman coding for optimization of test data compression, test application time and area overhead. J Electron Test 26(6):679–688CrossRef
17.
go back to reference Mehta US, Dasgupta KS, Devashrayee N (2010).Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. In proceeding 23rd International Conference on VLSI Design, pp: 33–38 Mehta US, Dasgupta KS, Devashrayee N (2010).Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes. In proceeding 23rd International Conference on VLSI Design, pp: 33–38
18.
go back to reference Miyase K, Kajihara S, Reddy SM (2004) Multiple scan tree design with test vector modification. In Proceedings IEEE Asian test symposium (ATS), pp 76–81 Miyase K, Kajihara S, Reddy SM (2004) Multiple scan tree design with test vector modification. In Proceedings IEEE Asian test symposium (ATS), pp 76–81
19.
go back to reference Mrugalski G, Rajski J, Tyszer J (2004) Ring generators–new devices for embedded test applications. IEEE Trans Comput Aided Des Integr Circuits Syst 23(9):1306–1320CrossRef Mrugalski G, Rajski J, Tyszer J (2004) Ring generators–new devices for embedded test applications. IEEE Trans Comput Aided Des Integr Circuits Syst 23(9):1306–1320CrossRef
20.
go back to reference Rajski J, Tyszer J, Kassab M, Mukherjee N (2004) Embedded deterministic test. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):776–792CrossRef Rajski J, Tyszer J, Kassab M, Mukherjee N (2004) Embedded deterministic test. IEEE Trans Comput Aided Des Integr Circuits Syst 23(5):776–792CrossRef
21.
go back to reference Ramm P, Armin K, Josef W, Maaike M, Taklo V (2010) 3D system-on-chip technologies for more than moore systems. Microsyst Technol 6:1051–1055CrossRef Ramm P, Armin K, Josef W, Maaike M, Taklo V (2010) 3D system-on-chip technologies for more than moore systems. Microsyst Technol 6:1051–1055CrossRef
22.
go back to reference Ruan X, Katti R.(2006) An efficient data-independent technique for compressing test vectors in systems-on-a-chip. In: Proceedings IEEE Computer Society Annual Symposium on Emerging VLSI technologies and architectures (ISVLSI), pp 153–158 Ruan X, Katti R.(2006) An efficient data-independent technique for compressing test vectors in systems-on-a-chip. In: Proceedings IEEE Computer Society Annual Symposium on Emerging VLSI technologies and architectures (ISVLSI), pp 153–158
23.
go back to reference Sivanantham S, Padmavathy M, Gopakumar G, Mallick PS, Perinbam JRP (2014) Enhancement of test data compression with multistage encoding. J Integ VLSI J 47:499–509CrossRef Sivanantham S, Padmavathy M, Gopakumar G, Mallick PS, Perinbam JRP (2014) Enhancement of test data compression with multistage encoding. J Integ VLSI J 47:499–509CrossRef
24.
go back to reference Tehranipoor M, Nourani M, Chakrabarty K (2005) Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans Very Large Scale Integ (Vlsi) Syst 13(6):719–731CrossRef Tehranipoor M, Nourani M, Chakrabarty K (2005) Nine-coded compression technique for testing embedded cores in SoCs. IEEE Trans Very Large Scale Integ (Vlsi) Syst 13(6):719–731CrossRef
25.
go back to reference Tenentes V, Kavousianos X, Kalligeros E (2010) Single and variable-state-skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores. IEEE Trans Comput Aided Des Integr Circuits Syst 29(2):1640–1644CrossRef Tenentes V, Kavousianos X, Kalligeros E (2010) Single and variable-state-skip LFSRs: bridging the gap between test data compression and test set embedding for IP cores. IEEE Trans Comput Aided Des Integr Circuits Syst 29(2):1640–1644CrossRef
26.
go back to reference Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303CrossRef Touba NA (2006) Survey of test vector compression techniques. IEEE Des Test Comput 23(4):294–303CrossRef
27.
go back to reference Tseng W-D, Lee L-J (2010) Test data compression using multi-dimensional pattern run-length codes. J Electron Test 226:393–400CrossRef Tseng W-D, Lee L-J (2010) Test data compression using multi-dimensional pattern run-length codes. J Electron Test 226:393–400CrossRef
28.
go back to reference Wang L., Wen X, Furukawa H., Hsu F. Lin S.,Tsai S.,Abdel-hafez K.S, Wu S. (2004). Virtual Scan: A new compressed scan technology for test cost reduction. In Proceedings IEEE international test conference (ITC), pp 916–925 Wang L., Wen X, Furukawa H., Hsu F. Lin S.,Tsai S.,Abdel-hafez K.S, Wu S. (2004). Virtual Scan: A new compressed scan technology for test cost reduction. In Proceedings IEEE international test conference (ITC), pp 916–925
30.
go back to reference Yang JS, Lee J, Touba NA (2014) Utilizing ATE Vector repeat with linear decompressor for test vector compression. IEEE Trans Comput-Aided Des Integ Circuits Syst 33(8):1219–1230CrossRef Yang JS, Lee J, Touba NA (2014) Utilizing ATE Vector repeat with linear decompressor for test vector compression. IEEE Trans Comput-Aided Des Integ Circuits Syst 33(8):1219–1230CrossRef
31.
go back to reference Yi M, Liang H, Zhang L, Zhan W (2010) A novel x-ploiting strategy for improving performance of test data compression. IEEE Trans VLSI Syst 18(2):324–329CrossRef Yi M, Liang H, Zhang L, Zhan W (2010) A novel x-ploiting strategy for improving performance of test data compression. IEEE Trans VLSI Syst 18(2):324–329CrossRef
32.
go back to reference Yuan H, Mei J, Song H, Guo K (2014) Test data compression for system-on-a-chip using count compatible pattern Run-length coding. J Electron Test 30:237–242CrossRef Yuan H, Mei J, Song H, Guo K (2014) Test data compression for system-on-a-chip using count compatible pattern Run-length coding. J Electron Test 30:237–242CrossRef
33.
go back to reference Zhou B, Y-Zheng Y, Li Z, Zhang J, Wu X, Ke R (2010) A test set embedding approach based on twisted-ring counter with few seeds. Integr VLSI J 43:81–100CrossRef Zhou B, Y-Zheng Y, Li Z, Zhang J, Wu X, Ke R (2010) A test set embedding approach based on twisted-ring counter with few seeds. Integr VLSI J 43:81–100CrossRef
Metadata
Title
Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression
Authors
Harpreet Vohra
Amardeep Singh
Publication date
26-10-2016
Publisher
Springer US
Published in
Journal of Electronic Testing / Issue 6/2016
Print ISSN: 0923-8174
Electronic ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-016-5617-x

Other articles of this Issue 6/2016

Journal of Electronic Testing 6/2016 Go to the issue

EditorialNotes

Editorial