The ELFNET Book on Failure Mechanisms, Testing Methods, and Quality Issues of Lead-Free Solder Interconnects

Cyclic load generally leads to mechanical failure of a material. In cyclic load, the load applied to a specimen varies in time and magnitude. This variation of load and time can be regular or stochastic. The effect of purely stochastic variations cannot be predicted; thus, the analysis of a cyclic load is done by simplifications trying to find a regular pattern in the load/time history. For the degradation behaviour, it makes a difference whether a specimen is subject to a slow variation of the load or to a rapid one. The two load regimes are assigned as low-cycle fatigue and high-cycle fatigue, respectively. In low-cycle fatigue, the time in each cycle allows the material to deform plastically, usually by creep. This means in low-cycle fatigue, the failure is triggered by deformation. High-cycle fatigue on the other hand does not leave enough time for relaxation. Local defects lead to local stress concentration above the yield strength, which causes the defect to grow with each cycle. In other words, high-cycle fatigue is stress driven. Usually, in high-cycle fatigue, the number of cycles to failure is above 10⁵ cycles. In reality, it is quite common that both kinds of fatigue are present, which makes testing for cyclic load quite complex.

This chapter mainly addresses the factors affecting the bulk embrittlement of Sn-based Pb-free solder joints, as this type of embrittlement may occur during the life cycle of these solder joints, depending on the requirements of their ‘mission profile’. The term ‘bulk embrittlement’ is used to describe brittle failures occurring in the solder bulk, in contrast to the brittle failures that occur in the intermetallic layers at the solder joint/bond pad interface. The factors affecting the bulk embrittlement of Sn-based Pb-free solder joints may be divided into ‘intrinsic’ and ‘extrinsic’. Examples of ‘intrinsic’ factors include the solder composition, crystal structure, and microstructure, while examples of ‘extrinsic’ factors include the temperature, strain rate, and constraint of the solder during service, as well as the cooling rate from the processing temperature. By understanding the mechanism of bulk solder embrittlement and the factors affecting it, one may try to find the ways to control it, especially when the conditions of the end application favour such type of embrittlement.

Solder low-cycle fatigue damage caused by temperature changes is one major reliability concern in electronics. In the paper, two fundamental approaches to characterize the solder joint fatigue resistance are introduced: testing and theoretical modelling. Thermal test cycling, which is applied to the majority of electronic products, is discussed in more detail and reference to different standards is made. Additionally, theoretical modelling based on analytical estimates as well as on numerical models, i.e. finite element models, is briefly introduced.

For a powered circuit, a metal corrosion–induced failure mechanism of particular concern is that of the formation of metal dendrites in the presence of contamination and moisture residues, which can lead to catastrophic failure. The propensities of two lead-free solders, SnAgCu (SAC) and Sn, to form dendrites have been assessed using electrochemical impedance (EI) technique and surface Insulation resistance (SIR) measurement, and benchmarked against the performance of conventional SnPb alloy. Two PCB finish materials (Cu and ENIG) have been also investigated for comparison. The dendrites formed from different metals were analysed using SEM-EDX equipment. The work has shown that dendrite formation occurs more readily with the SnPb solder than with the SAC and Sn solders due to the high corrosion rate of Pb in the Pb in SbPb alloy, and/or high solubility of Pb(OH)_2. In contrast, the low propensity to form dendrite for Cu finish board compared with ENIG finish suggests its low corrosion rate and low solubility of Cu(OH)₂. The good correlation of ionic resistance measured in the EI results and the propensities of metal to form dendrite indicates that metal corrosion rate and the solubility of metal play a major role in dendrite formation.

From experiments by Smigelskas and Kirkendall [1], it was demonstrated that in a binary solution the rates at which the two types of atoms diffuse are not the same. Due to this phenomenon, it has frequently been observed that voids, or pores, form in the region of the diffusion zone from which there is a flow of mass. The formation of these voids strongly influences the mechanical properties. The Kirkendall experiment studied the diffusion of zinc and copper. Similar results have been found for a large range of binary alloys. In soldered joints, due to diffusion at the interfaces solder/substrate, void formation has been observed. For the new lead free solder alloys, the details of void formation by the Kirkendall effect have not been studied in great detail. Although a large amount of data are published, a comprehensive and detailed overview is lacking. Different researchers employ different process condition (reflow temperature and time, number of reflows, annealing temperature and time), which makes the comparison difficult. In general, only a reference is made to the occurrence of Kirkendall voids. In the first part of this paper, the principles of diffusion and the Kirkendall effect will be briefly described. This is followed by the mechanism of void formation. Finally, the effects in soldered joints will be discussed for a number of solder systems, which experience void formation by the Kirkendall effect.

Pure tin is currently the most widely employed lead-free finish for plating of component terminals despite its propensity to spontaneous whisker formation. Whiskers are filamentary crystals, conductive and mechanically strong, measuring up to a few millimetres, though the common variety observed on matt tin finish on copper substrate was hardly ever reported to exceed 0.5 mm. A positive stress gradient within the Sn layer, that is either a lowering compressive or an increasing tensile stress towards the root of a whisker, is reputed as the driving force for whisker formation. The formation of whisker is a major reliability concern for the electronic industry. Whisker-related failures in electric and electronic hardware have been reported since the 1940, and the failure risk cannot be overlooked especially in modern electronic systems. Understanding the tin whisker phenomenon and further developing mitigation strategies and test methods for evaluating whisker performance are all important tasks to be fulfilled in the future.

The scaling down of microelectronic circuits (ITRS Roadmap) and increasing functionality inevitably leads to smaller bond pads, smaller pitches and smaller diameters for the solder flip chip interconnections. This not only compromises the mechanical integrity of the joint, a smaller contact pad will also lead to an increased current density enhancing the risk for electromigration. This work provides some guidelines to perform solder bump electromigration testing. The experimental settings are shown to have a large effect on the failure modes and according failure analysis. A test case comparing the electromigration behaviour of two different under bump metallurgy–solder interfaces, being Cu–Sn and Cu/Ni/Au–Sn, is given. A special test structure that allows the separate measurement of the anodic and cathodic bump interface is introduced.

Solder joints to solder lands plated with electroless nickel and immersion gold are prone to fractures in the interface between the solder and the nickel surface. A common cause for these fractures has been a plating defect in the solder land coating called “black pad”. However, solder joints to solder lands plated with electroless nickel are inclined to fractures even if the black pad defect is not present. The causes of the black pad defect and the mechanisms for the increased inclination for fractures in solder joints to electroless nickel are discussed. Test methods for detecting black pad defects and assessing the risk for fractures in the solder joints are also described.

The emphasis of this chapter is placed on describing the loading condition under drop testing of electronic devices and the analysis of the failure modes and mechanisms of high-density component boards under mechanical shock loading conditions. The failure modes and mechanisms under drop impact loading are markedly different from those typically observed in thermally cycled component boards. Reliability of different material combinations under the tests is reported, and the associated failure modes and mechanisms are discussed. Because the reliability of electronic assemblies under mechanical shock loading is highly dependent on the ability of intermetallic layers to withstand the stresses produced during drop impacts, the formation and properties of different interfacial regions are discussed in detail. Furthermore, it is shown that alloying and impurity elements can have strong effects on the intermetallic layers in the solder interconnections and the drop reliability of component boards.

Many electronics products are used in humid environments. High humidity in combination with various contaminants will affect the surface insulation resistance on printed board assemblies and may cause current leakage or in worse case short circuit due to electrochemical migration. This chapter discusses the failure mechanism for electrochemical migration and how it is affected by common contaminants on assemblies. Test methods for measuring surface insulation resistance and for assessing the risk for electrochemical migration are reviewed, and their relevance is discussed.

Conductive anodic filamentation is a subsurface failure mode in woven glass-reinforced laminate (FR4) materials, where a copper salt filament allows bridging between via walls and other copper conductors. In this study, FR4 laminates, in the form of high-via-density multilayer test circuits, are exposed to different manufacturing conditions and assessed for resistance to conductive anodic filamentation (CAF). CAF performance was assessed using high temperature and humidity conditions to promote failures, with a voltage applied across adjacent via. By the application of a range of voltages and via geometries, a performance map for laminates can be obtained to compare materials for performance. The changes due to exposure of laminate to tin–lead and lead-free temperatures are then examined using the technique.

Delamination is not only a problem with lead-free soldering but since the problem accelerates with heat, it has been more common, and therefore extra care has to be taken. The design and material choice have a major impact of the delamination risk for a board. It is important to order lead-free boards and if possible avoid buried vias and reduce large copper planes. Another important design aspect is the placement of components. A low delta T during soldering will reduce risk of delamination.

During a solder reflow process, IC components deform under a rather excessive temperature loading. A too high warpage at temperatures above solder melting can cause either that the joints in the corner are not soldered to the PCB pads or that the solder joints are shorted due to strong compression of the corner joints. In this work, the warpage of a 35 by 35 mm² large PBGA package has been measured during a temperature profile, which is similar to a lead-free soldering process. It was found that the warpage becomes very high when the applied temperature is above the glass transition temperature of the overmould material. At that moment, there exists a very large CTE mismatch between the overmould and the BT laminate. The warpage measurements have been successfully verified by Finite Element Modelling, at least when the right material properties are used. This proves that modelling can be used as an estimator of warpage for packages. Also the impact of initial moisture uptake has been experimentally investigated, and it was shown that it has a dominant effect on its warpage behaviour. Finally, a FEM-based parametric study shows the impact of several design parameters.

Interface delamination and popcorn cracking are among the most common reasons for mechanical damage in plastic packaging. Many investigations have shown the popcorn phenomenon to be a closely linked process of delamination of the pad/encapsulant interface, moisture diffusion, vapor pressure build-up, and popcorn cracking. A short survey on the phenomenon is given.

For surface mount components, the most used alloy family for reflow soldering, the SnAgCu, shows a liquidus temperature ranging between 217 and 221°C, and it is agreed that during reflow the coldest solder joint temperature should be no less than 230°C. Accordingly, the components are submitted to temperatures notably higher than those to which they were submitted with the Pb technology and much of them had to be re-qualified. What can one say today in connection with the thermal compatibility of components with the lead-free soldering processes? To answer this question, we examined more than 125 web sites of components makers and we also learned from the members of the Components Technical Experts Group. The obtained results are exposed below by distinguishing active and passive components.