Issue 2/1998
Content (11 Articles)
Design for Testability Techniques at the Behavioral and Register-Transfer Levels
Sujit Dey, Anand Raghunathan, Kenneth D. Wagner
High-Level Controllability and Observability Analysis for Test Synthesis
Frank F. Hsu, Janak H. Patel
RTL Test Justification and Propagation Analysis for Modular Designs
Yiorgos Makris, Alex Orailogcaron;lu
Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays
Li-C. Wang, Magdy S. Abadir
Allocation Techniques for Reducing BIST Area Overhead of Data Paths
Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer
High-Level Test Synthesis for Behavioral and Structural Designs
Christos A. Papachristou, Mikhail Baklashov, Kowen Lai
Versatile BIST: An Integrated Approach to On-line/Off-line BIST for Data-Dominated Architectures
Nilanjan Mukherjee, Ramesh Karri
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey