Issue 3/2015
Content (10 Articles)
A Unified Sequential Equivalence Checking Methodology to Verify RTL Designs with High-Level Functional and Protocol Specification Models
Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch
Marko S. Andjelković, Vladimir Petrović, Zoran Stamenković, Goran S. Ristić, Goran S. Jovanović
A Hilbert-Transform-Based Method to Estimate and Correct Timing Error in Time-Interleaved ADCs
Li Wang, Lianping Guo, Jun Jiang, Duyu Qiu
A New Approach to Model the Effect of Topology on Testing Using Boundary Scan
Farnaz Fotovatikhah, Bahareh Naraghi, Fatemeh Tavakoli, Mahdiar Ghadiry
Distributed Scan Like Fault Detection and Test Optimization for Digital Microfluidic Biochips
Subhamita Mukherjee, Tuhina Samanta
One More Class of Sequential Circuits having Combinational Test Generation Complexity
Debesh Kumar Das, Hideo Fujiwara
A New On-chip Signal Generator for Charge-Based Capacitance Measurement Circuit
Xiao Peng Yu, Rong Qian Tian, Wen Lin Xu, Zheng Shi