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Erschienen in:
Anatomy of the Focal-Plane Sensor-Processor Arrays Kapitel lesen Erstes Kapitel lesen

2011 | OriginalPaper | Buchkapitel

A Focal Plane Processor for Continuous-Time 1-D Optical Correlation Applications

verfasst von : Gustavo Liñán-Cembrano, Luis Carranza, Betsaida Alexandre, Ángel Rodríguez-Vázquez, Pablo de la Fuente, Tomás Morlanes

Erschienen in: Focal-Plane Sensor-Processor Chips

Verlag: Springer New York

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Abstract

This chapter describes a 1-D Focal Plane Processor, which has been designed to run continuous-time optical correlation applications. The chip contains 200 sensory processing elements, which acquire light patterns through a 2mm ×10.9μm photodiode. The photogenerated current is scaled at the pixel level by five independent 3-bit programmable-gain current scaling blocks. The correlation patterns are defined as five sets of two hundred 3-bit numbers (from 0 to 7), which are provided to the chip through a standard I2C interface. Correlation outputs are provided in current form through 8-bit programmable gain amplifiers (PGA), whose configurations are also defined via I2C. The chip contains a mounting alignment help, which consists of three rows of 100 conventional active pixel sensors (APS) inserted at the top, middle and bottom part of the main photodiode array. The chip has been fabricated in a standard 0.35μm CMOS technology and its maximum power consumption is below 30mW. Experimental results demonstrate that the chip is able to process interference patterns moving at an equivalent frequency of 500kHz.

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Vorheriges Kapitel A Biomimetic Frame-Free Event-Driven Image Sensor
Nächstes Kapitel VISCUBE: A Multi-Layer Vision Chip
Fußnoten
1
λ=880nm in our case.
 
2
Which is approximately equivalent – neglecting partial suppression of reset noise due to averaging – to acquire the image with a 1D-CCD whose pixels have the same height as the array.
 
3
Indeed, movement is amplified at the focal plane due to the optical setup of the system.
 
4
Precisely means errors below 1μm per meter in this case.
 
5
Which indeed corresponds to the displacement of the object.
 
6
Using four periods of fringes and having relative prime numbers in diode’s pitch and fringe period improves the quality of the interpolation process over the Lissajous plot when measuring the displacement.
 
7
Nominal frequency of the designed token ring oscillator; process corners, mismatching, power supply variations, and temperature affect this frequency which might move±50%.
 
8
A reset commanded by the user by pulling down the RST pin of the chip.
 
9
Due to this direct connection, we could get big current peaks during programming since we are moving all bits in the shift register every clock cycle. To avoid this, the analogue part of the chip can be switched off during the programming phase by asserting a particular bit in CRF20. Indeed, by default – i.e., after power-on or reset –, this bit is set to 0, to avoid any kind of trouble with this issue, and the user is always requested to activate the analogue part of the chip to get some current through its outputs. This option does not switch off the three rows of APS pixels, and nor their output amplifiers, thus allowing to get information about correct positioning of the chip during the mounting of the head without needing to activate the five correlation outputs.
 
10
We use the NMOS version for simplicity – i.e., not including VDD in the equations.
 
11
\({V }_{\mathrm{GE}} = {V }_{\mathrm{GS}} - {V }_{\mathrm{TH}}\).
 
12
Since degradation of performance beyond the optimum is quite abrupt – the PMOS input transistor of the mirror leaves the saturation region –, we preferred to move a little bit from the optimum value.
 
13
Indeed, this offset voltage plays the same role as a variation in the threshold voltage of input transistors in the programmable current sources.
 
14
Assuming, for simplicity, that we are not using I BIAS.
 
15
Or, equivalently, the number of unitary current sources connected in parallel in this SPE to this accumulation node.
 
16
It will make voltage at the input node to go above the limit imposed by the amplifier (V sense), producing an instability in the circuitry due to the continuous transition from cut-off to conduction of the transistor in the feedback loop.
 
17
See footnote 16.
 
18
This situation is not very likely though. Considering that the average coefficient in each correlation channel is around 3 that the maximum expected photogenerated current is about 300nA (very optimistic supposition), and that we have 200 SPEs, the maximum expected output channel would be 180μA.
 
19
Although we can transmit byte by byte the information to be written in the FIFO from the PC via RS232 to the PIC and from the PIC to the chip, we have implemented a faster method by defining some preloaded FIFO configurations in the PIC memory so that one can simply select the configuration to with which write into the chip instead of transmitting it from the computer.
 
20
Indeed, we read 200 ×30nA=6μA.
 
21
Surprisingly, when we use the buffer and I BIAS the resulting error is smaller due to their different signs. Indeed, adding I BIAS introduces a small systematic offset – due to non-total suppression of the I BIAS in the SPE output current – which somehow compensates the small systematic – obviously not the random, but we observe averaged results since we measure the current from 200 SPEs – component of the offset voltage of the buffer. Besides, this compensation is observed independently of the implemented coefficient since both terms scale as a function of the number of current sources connected to the SPE output node.
 
22
This is the worst case since we are programming the maximum capacitive load.
 
Literatur
1.
2.
D. Crespo, P. Alonso, T. Morlanes, E. Bernabeu, Opt. Eng. 39, 817 (2000)CrossRef
3.
D. Crespo, Nuevas herramientas aplicadas a la codificación óptica. Ph.D. thesis, Univ. Complutense de Madrid (2001)
4.
T. Morlanes, Optical length measuring device with optoelectronic arrangement of photodetectors. European Patent Specification EP1164359B1
5.
6.
H.F. Talbot, Philos. Mag. 9, 401–407 (1836)
7.
Metadaten
Titel
A Focal Plane Processor for Continuous-Time 1-D Optical Correlation Applications
verfasst von
Gustavo Liñán-Cembrano
Luis Carranza
Betsaida Alexandre
Ángel Rodríguez-Vázquez
Pablo de la Fuente
Tomás Morlanes
Copyright-Jahr
2011
Verlag
Springer New York
Buch
Focal-Plane Sensor-Processor Chips

Print ISBN: 978-1-4419-6474-8

Electronic ISBN: 978-1-4419-6475-5

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4419-6475-5_7

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