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Erschienen in:
2005 | OriginalPaper | Buchkapitel
A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture
verfasst von : Jin-Ho Ahn, Byung In Moon, Sungho Kang
Erschienen in: Advances in Computer Systems Architecture
Verlag: Springer Berlin Heidelberg
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It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC’02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 – 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.