Skip to main content

2016 | OriginalPaper | Buchkapitel

A Review of Image Interest Point Detectors: From Algorithms to FPGA Hardware Implementations

verfasst von : Cesar Torres-Huitzil

Erschienen in: Image Feature Detectors and Descriptors

Verlag: Springer International Publishing

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Fast and accurate image feature detectors are an important challenge in computer vision as they are the basis for high-level image processing analysis and understanding. However, image feature detectors cannot be easily applied in real-time embedded computing scenarios, such as autonomous robots and vehicles, mainly due to the fact that they are time consuming and require considerable computational resources. For embedded and low power devices, speed and memory efficiency is of main concern, and therefore, there have been several recent attempts to improve this performance gap through dedicated hardware implementations of feature detectors. Thanks to the fine grain massive parallelism and flexibility of software-like methodologies, reconfigurable hardware devices, such as Field Programmable Gate Arrays (FPGAs), have become a common choice to speed up computations. In this chapter, a review of hardware implementations of feature detectors using FPGAs targeted to embedded computing scenarios is presented. The necessary background and fundamentals to introduce feature detectors and their mapping to FPGA-based hardware implementations are presented. Then we provide an analysis of some relevant state-of-the-art hardware implementations, which represent current research solutions proposed in this field. The review addresses a broad range of techniques, methods, systems and solutions related to algorithm-to-hardware mapping of image interest point detectors. Our goal is not only to analyze, compare and consolidate past research work but also to appreciate their findings and discuss their applicability. Some possible directions for future research are presented.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Literatur
1.
Zurück zum Zitat Schmid, C., Mohr, R., Bauckhage, C.: Evaluation of interest point detectors. Int. J. Comput. Vision 37(2), 151–172 (2000)CrossRefMATH Schmid, C., Mohr, R., Bauckhage, C.: Evaluation of interest point detectors. Int. J. Comput. Vision 37(2), 151–172 (2000)CrossRefMATH
2.
Zurück zum Zitat Dorko, G., Schmid, C.: Selection of scale-invariant parts for object class recognition. In: Ninth IEEE International Conference on Computer Vision. Proceedings, vol. 1, pp. 634–639 (2003) Dorko, G., Schmid, C.: Selection of scale-invariant parts for object class recognition. In: Ninth IEEE International Conference on Computer Vision. Proceedings, vol. 1, pp. 634–639 (2003)
3.
Zurück zum Zitat Lazebnik, S., Schmid, C., Ponce, J.: Affine-invariant local descriptors and neighborhood statistics for texture recognition. In: Ninth IEEE International Conference on Computer Vision. Proceedings, vol. 1, pp. 649–655 (2003) Lazebnik, S., Schmid, C., Ponce, J.: Affine-invariant local descriptors and neighborhood statistics for texture recognition. In: Ninth IEEE International Conference on Computer Vision. Proceedings, vol. 1, pp. 649–655 (2003)
4.
Zurück zum Zitat Brown, M., Lowe, D.G.: Automatic panoramic image stitching using invariant features. Int. J. Comput. Vis. 74(1), 59–73 (2007)CrossRef Brown, M., Lowe, D.G.: Automatic panoramic image stitching using invariant features. Int. J. Comput. Vis. 74(1), 59–73 (2007)CrossRef
5.
Zurück zum Zitat Wang, X., pan Niu, P., ying Yang, H., li Chen, L.: Affine invariant image watermarking using intensity probability density-based harris laplace detector. J. Vis. Commun. Image Represent. 23(6), 892–907 (2012) Wang, X., pan Niu, P., ying Yang, H., li Chen, L.: Affine invariant image watermarking using intensity probability density-based harris laplace detector. J. Vis. Commun. Image Represent. 23(6), 892–907 (2012)
6.
Zurück zum Zitat Ebrahimi, M., Mayol-Cuevas, W.: Adaptive sampling for feature detection, tracking, and recognition on mobile platforms. IEEE Trans. Circuits Syst. Video Technol. 21(10), 1467–1475 (2011)CrossRef Ebrahimi, M., Mayol-Cuevas, W.: Adaptive sampling for feature detection, tracking, and recognition on mobile platforms. IEEE Trans. Circuits Syst. Video Technol. 21(10), 1467–1475 (2011)CrossRef
8.
Zurück zum Zitat Guerra-Filho, G.: An iterative combination scheme for multimodal visual feature detection. Neurocomputing 120, 346–354 (2013)CrossRef Guerra-Filho, G.: An iterative combination scheme for multimodal visual feature detection. Neurocomputing 120, 346–354 (2013)CrossRef
9.
Zurück zum Zitat Hernandez-Lopez, A., Torres-Huitzil, C., Garcia-Hernandez, J.: Fpga-based flexible hardware architecture for image interest point detection. Int. J. Adv. Robot. Syst. 12(93), 1–15 (2015)CrossRef Hernandez-Lopez, A., Torres-Huitzil, C., Garcia-Hernandez, J.: Fpga-based flexible hardware architecture for image interest point detection. Int. J. Adv. Robot. Syst. 12(93), 1–15 (2015)CrossRef
10.
Zurück zum Zitat Torres-Huitzil, C., Arias-Estrada, M.: FPGA-based configurable systolic architecture for window-based image processing. EURASIP J. Adv. Sig. Proc. 2005(7), 1024–1034 (2005)CrossRefMATH Torres-Huitzil, C., Arias-Estrada, M.: FPGA-based configurable systolic architecture for window-based image processing. EURASIP J. Adv. Sig. Proc. 2005(7), 1024–1034 (2005)CrossRefMATH
11.
Zurück zum Zitat Lim, Y., Kleeman, L., Drummond, T.: Algorithmic methodologies for FPGA-based vision. Mach. Vis. Appl. 24(6), 1 (2013)CrossRef Lim, Y., Kleeman, L., Drummond, T.: Algorithmic methodologies for FPGA-based vision. Mach. Vis. Appl. 24(6), 1 (2013)CrossRef
12.
Zurück zum Zitat Tippetts, B., Lee, D.J., Archibald, J.: An on-board vision sensor system for small unmanned vehicle applications. Mach. Vis. Appl. 23(3), 403–415 (2012)CrossRef Tippetts, B., Lee, D.J., Archibald, J.: An on-board vision sensor system for small unmanned vehicle applications. Mach. Vis. Appl. 23(3), 403–415 (2012)CrossRef
13.
Zurück zum Zitat Park, I.K., Singhal, N., Lee, M.H., Cho, S., Kim, C.: Design and performance evaluation of image processing algorithms on GPUs. IEEE Trans. Parallel Distrib. Syst. 22(1), 91–104 (2011)CrossRef Park, I.K., Singhal, N., Lee, M.H., Cho, S., Kim, C.: Design and performance evaluation of image processing algorithms on GPUs. IEEE Trans. Parallel Distrib. Syst. 22(1), 91–104 (2011)CrossRef
14.
Zurück zum Zitat Pauwels, K., Tomasi, M., Diaz Alonso, J., Ros, E., Van Hulle, M.: A comparison of FPGA and GPU for real-time phase-based optical flow, stereo, and local image features. IEEE Trans. Comput. 61(7), 999–1012 (2012)CrossRefMathSciNet Pauwels, K., Tomasi, M., Diaz Alonso, J., Ros, E., Van Hulle, M.: A comparison of FPGA and GPU for real-time phase-based optical flow, stereo, and local image features. IEEE Trans. Comput. 61(7), 999–1012 (2012)CrossRefMathSciNet
15.
Zurück zum Zitat Andreopoulos, Y., Patras, I.: Incremental refinement of image salient-point detection. IEEE Trans. Image Process. 17(9), 1685–1699 (2008)CrossRefMathSciNet Andreopoulos, Y., Patras, I.: Incremental refinement of image salient-point detection. IEEE Trans. Image Process. 17(9), 1685–1699 (2008)CrossRefMathSciNet
16.
Zurück zum Zitat Awrangjeb, M., Lu, G., Fraser, C.: Performance comparisons of contour-based corner detectors. IEEE Trans. Image Process. 21(9), 4167–4179 (2012)CrossRefMathSciNet Awrangjeb, M., Lu, G., Fraser, C.: Performance comparisons of contour-based corner detectors. IEEE Trans. Image Process. 21(9), 4167–4179 (2012)CrossRefMathSciNet
17.
Zurück zum Zitat Bostanci, E., Kanwal, N., Clark, A.: Spatial statistics of image features for performance comparison. IEEE Trans. Image Process. 23(1), 153–162 (2014)CrossRefMathSciNet Bostanci, E., Kanwal, N., Clark, A.: Spatial statistics of image features for performance comparison. IEEE Trans. Image Process. 23(1), 153–162 (2014)CrossRefMathSciNet
18.
Zurück zum Zitat Olague, G., Trujillo, L.: Interest point detection through multiobjective genetic programming. Appl. Soft Comput. 12(8), 2566–2582 (2012)CrossRef Olague, G., Trujillo, L.: Interest point detection through multiobjective genetic programming. Appl. Soft Comput. 12(8), 2566–2582 (2012)CrossRef
19.
Zurück zum Zitat Canny, J.: A computational approach to edge detection. IEEE Trans. Pattern Anal. Mach. Intell. 8(6), 679–698 (1986)CrossRef Canny, J.: A computational approach to edge detection. IEEE Trans. Pattern Anal. Mach. Intell. 8(6), 679–698 (1986)CrossRef
20.
Zurück zum Zitat Smith, S.M., Brady, J.M.: SUSAN—a new approach to low level image processing. Int. J. Comput. Vis. 23, 45–78 (1997)CrossRef Smith, S.M., Brady, J.M.: SUSAN—a new approach to low level image processing. Int. J. Comput. Vis. 23, 45–78 (1997)CrossRef
21.
Zurück zum Zitat Harris, C., Stephens, M.: A combined corner and edge detector. In: In Proceedings of the 4th Alvey Vision Conference, pp. 147–151 (1988) Harris, C., Stephens, M.: A combined corner and edge detector. In: In Proceedings of the 4th Alvey Vision Conference, pp. 147–151 (1988)
22.
Zurück zum Zitat Rosten, E., Drummond, T.: Machine learning for high-speed corner detection. In: Proceedings of the 9th European Conference on Computer Vision—Volume Part I, pp. 430–443. ECCV’06, Springer, Berlin (2006) Rosten, E., Drummond, T.: Machine learning for high-speed corner detection. In: Proceedings of the 9th European Conference on Computer Vision—Volume Part I, pp. 430–443. ECCV’06, Springer, Berlin (2006)
23.
Zurück zum Zitat Bay, H., Ess, A., Tuytelaars, T., Gool, L.V.: Speeded-up robust features (SURF). Comput. Vis. Image Underst. 110(3), 346–359 (2008), similarity Matching in Computer Vision and Multimedia Bay, H., Ess, A., Tuytelaars, T., Gool, L.V.: Speeded-up robust features (SURF). Comput. Vis. Image Underst. 110(3), 346–359 (2008), similarity Matching in Computer Vision and Multimedia
24.
Zurück zum Zitat Lowe, D.: Object recognition from local scale-invariant features. In: The Proceedings of the Seventh IEEE International Conference on Computer Vision, vol. 2, pp. 1150–1157 (1999) Lowe, D.: Object recognition from local scale-invariant features. In: The Proceedings of the Seventh IEEE International Conference on Computer Vision, vol. 2, pp. 1150–1157 (1999)
26.
Zurück zum Zitat Toledo-Moreo, F.J., Martinez-Alvarez, J.J., Garrigos-Guerrero, J., Ferrandez-Vicente, J.M.: FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size. J. Syst. Architect. 58(8), 277–285 (2012)CrossRef Toledo-Moreo, F.J., Martinez-Alvarez, J.J., Garrigos-Guerrero, J., Ferrandez-Vicente, J.M.: FPGA-based architecture for the real-time computation of 2-D convolution with large kernel size. J. Syst. Architect. 58(8), 277–285 (2012)CrossRef
27.
Zurück zum Zitat Torres-Huitzil, C.: Fast hardware architecture for grey-level image morphology with flat structuring elements. Image Process., IET 8(2), 112–121 (2014)CrossRef Torres-Huitzil, C.: Fast hardware architecture for grey-level image morphology with flat structuring elements. Image Process., IET 8(2), 112–121 (2014)CrossRef
28.
Zurück zum Zitat Hedberg, H., Kristensen, F., Wall, V.: Low-complexity binary morphology architectures with flat rectangular structuring elements. IEEE Trans. Circuits Syst. I: Regul. Pap. 55(8), 2216–2225 (2008) Hedberg, H., Kristensen, F., Wall, V.: Low-complexity binary morphology architectures with flat rectangular structuring elements. IEEE Trans. Circuits Syst. I: Regul. Pap. 55(8), 2216–2225 (2008)
29.
Zurück zum Zitat Girau, B., Torres-Huitzil, C.: Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation. Neurocomputing 70(79), 1186–1197 (2007) Girau, B., Torres-Huitzil, C.: Massively distributed digital implementation of an integrate-and-fire LEGION network for visual scene segmentation. Neurocomputing 70(79), 1186–1197 (2007)
30.
Zurück zum Zitat Rangel-Valdez, N., Barron-Zambrano, J.H., Torres-Huitzil, C., Torres-Jimenez, J.: An efficient fpga architecture for integer nth root computation. Int. J. Electron. 102(10), 1675–1694 (2015) Rangel-Valdez, N., Barron-Zambrano, J.H., Torres-Huitzil, C., Torres-Jimenez, J.: An efficient fpga architecture for integer nth root computation. Int. J. Electron. 102(10), 1675–1694 (2015)
31.
Zurück zum Zitat Barron-Zambrano, J.H., Torres-Huitzil, C.: FPGA implementation of a configurable neuromorphic CPG-based locomotion controller. Neural Netw. 45, 50–61 (2013)CrossRef Barron-Zambrano, J.H., Torres-Huitzil, C.: FPGA implementation of a configurable neuromorphic CPG-based locomotion controller. Neural Netw. 45, 50–61 (2013)CrossRef
32.
Zurück zum Zitat Monmasson, E., Cirstea, M.: FPGA design methodology for industrial control systems—a review. IEEE Trans. Industr. Electron. 54(4), 1824–1842 (2007)CrossRef Monmasson, E., Cirstea, M.: FPGA design methodology for industrial control systems—a review. IEEE Trans. Industr. Electron. 54(4), 1824–1842 (2007)CrossRef
33.
Zurück zum Zitat Hartley, E., Jerez, J., Suardi, A., Maciejowski, J., Kerrigan, E., Constantinides, G.: Predictive control using an FPGA with application to aircraft control. IEEE Trans. Control Syst. Technol. 22(3), 1006–1017 (2014)CrossRef Hartley, E., Jerez, J., Suardi, A., Maciejowski, J., Kerrigan, E., Constantinides, G.: Predictive control using an FPGA with application to aircraft control. IEEE Trans. Control Syst. Technol. 22(3), 1006–1017 (2014)CrossRef
34.
Zurück zum Zitat Chappet De Vangel, B., Torres-Huitzil, C., Girau, B.: Randomly spiking dynamic neural fields. J. Emerg. Technol. Comput. Syst. 11(4), 37:1–37:26 (2015) Chappet De Vangel, B., Torres-Huitzil, C., Girau, B.: Randomly spiking dynamic neural fields. J. Emerg. Technol. Comput. Syst. 11(4), 37:1–37:26 (2015)
35.
Zurück zum Zitat Torres-Huitzil, C., Delgadillo-Escobar, M., Nuno-Maganda, M.: Comparison between 2D cellular automata based pseudorandom number generators. IEICE Electron. Express 9(17), 1391–1396 (2012)CrossRef Torres-Huitzil, C., Delgadillo-Escobar, M., Nuno-Maganda, M.: Comparison between 2D cellular automata based pseudorandom number generators. IEICE Electron. Express 9(17), 1391–1396 (2012)CrossRef
36.
Zurück zum Zitat Trimberger, S.: Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc. IEEE 103(3), 318–331 (2015)CrossRef Trimberger, S.: Three ages of FPGAs: a retrospective on the first thirty years of FPGA technology. Proc. IEEE 103(3), 318–331 (2015)CrossRef
38.
Zurück zum Zitat Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., Zhang, Z.: High-level synthesis for fpgas: from prototyping to deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4), 473–491 (2011)CrossRef Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., Zhang, Z.: High-level synthesis for fpgas: from prototyping to deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4), 473–491 (2011)CrossRef
39.
Zurück zum Zitat Kumar Jaiswal, M., Chandrachoodan, N.: FPGA-based high-performance and scalable block LU decomposition architecture. IEEE Trans. Comput. 61(1), 60–72 (2012)CrossRefMathSciNet Kumar Jaiswal, M., Chandrachoodan, N.: FPGA-based high-performance and scalable block LU decomposition architecture. IEEE Trans. Comput. 61(1), 60–72 (2012)CrossRefMathSciNet
40.
Zurück zum Zitat Torres-Huitzil, C., Arias-Estrada, M.: An FPGA architecture for high speed edge and corner detection. In: Fifth IEEE International Workshop on Computer Architectures for Machine Perception. Proceedings, pp. 112–116 (2000) Torres-Huitzil, C., Arias-Estrada, M.: An FPGA architecture for high speed edge and corner detection. In: Fifth IEEE International Workshop on Computer Architectures for Machine Perception. Proceedings, pp. 112–116 (2000)
41.
Zurück zum Zitat Possa, P., Mahmoudi, S., Harb, N., Valderrama, C., Manneback, P.: A multi-resolution FPGA-based architecture for real-time edge and corner detection. IEEE Trans. Comput. 63(10), 2376–2388 (2014)CrossRefMathSciNet Possa, P., Mahmoudi, S., Harb, N., Valderrama, C., Manneback, P.: A multi-resolution FPGA-based architecture for real-time edge and corner detection. IEEE Trans. Comput. 63(10), 2376–2388 (2014)CrossRefMathSciNet
42.
Zurück zum Zitat Xu, Q., Varadarajan, S., Chakrabarti, C., Karam, L.: A distributed canny edge detector: algorithm and FPGA implementation. IEEE Trans. Image Process. 23(7), 2944–2960 (2014)CrossRefMathSciNet Xu, Q., Varadarajan, S., Chakrabarti, C., Karam, L.: A distributed canny edge detector: algorithm and FPGA implementation. IEEE Trans. Image Process. 23(7), 2944–2960 (2014)CrossRefMathSciNet
44.
Zurück zum Zitat Kraft, M., Schmidt, A., Kasinski, A.J.: High-speed image feature detection using FPGA implementation of fast algorithm. In: Ranchordas, A., Arajo, H. (eds.) VISAPP (1), pp. 174–179.INSTICC—Institute for Systems and Technologies of Information, Control and Communication (2008) Kraft, M., Schmidt, A., Kasinski, A.J.: High-speed image feature detection using FPGA implementation of fast algorithm. In: Ranchordas, A., Arajo, H. (eds.) VISAPP (1), pp. 174–179.INSTICC—Institute for Systems and Technologies of Information, Control and Communication (2008)
45.
Zurück zum Zitat Hsiao, P.Y., Lu, C.L., Fu, L.C.: Multilayered image processing for multiscale harris corner detection in digital realization. IEEE Trans. Industr. Electron. 57(5), 1799–1805 (2010)CrossRef Hsiao, P.Y., Lu, C.L., Fu, L.C.: Multilayered image processing for multiscale harris corner detection in digital realization. IEEE Trans. Industr. Electron. 57(5), 1799–1805 (2010)CrossRef
46.
Zurück zum Zitat Torres-Huitzil, C.: Resource efficient hardware architecture for fast computation of running max/min filters. Sci. World J. 2013, 1–10 (2013)CrossRef Torres-Huitzil, C.: Resource efficient hardware architecture for fast computation of running max/min filters. Sci. World J. 2013, 1–10 (2013)CrossRef
47.
Zurück zum Zitat Viola, P., Jones, M.: Rapid object detection using a boosted cascade of simple features. In: Proceedings of the 2001 IEEE Computer Society Conference on Computer Vision and Pattern Recognition. CVPR 2001, vol. 1, pp. I-511-I-518 (2001) Viola, P., Jones, M.: Rapid object detection using a boosted cascade of simple features. In: Proceedings of the 2001 IEEE Computer Society Conference on Computer Vision and Pattern Recognition. CVPR 2001, vol. 1, pp. I-511-I-518 (2001)
48.
Zurück zum Zitat Jiang, J., Li, X., Zhang, G.: SIFT hardware implementation for real-time image feature extraction. IEEE Trans. Circuits Syst. Video Technol. 24(7), 1209–1220 (2014)CrossRef Jiang, J., Li, X., Zhang, G.: SIFT hardware implementation for real-time image feature extraction. IEEE Trans. Circuits Syst. Video Technol. 24(7), 1209–1220 (2014)CrossRef
49.
Zurück zum Zitat Wang, J., Zhong, S., Yan, L., Cao, Z.: An embedded system-on-chip architecture for real-time visual detection and matching. IEEE Trans. Circuits Syst. Video Technol. 24(3), 525–538 (2014)CrossRef Wang, J., Zhong, S., Yan, L., Cao, Z.: An embedded system-on-chip architecture for real-time visual detection and matching. IEEE Trans. Circuits Syst. Video Technol. 24(3), 525–538 (2014)CrossRef
50.
Zurück zum Zitat Chang, L., Hernndez-Palancar, J., Sucar, L., Arias-Estrada, M.: FPGA-based detection of SIFT interest keypoints. Mach. Vis. Appl. 24(2), 371–392 (2013) Chang, L., Hernndez-Palancar, J., Sucar, L., Arias-Estrada, M.: FPGA-based detection of SIFT interest keypoints. Mach. Vis. Appl. 24(2), 371–392 (2013)
51.
Zurück zum Zitat Bonato, V., Marques, E., Constantinides, G.: A parallel hardware architecture for scale and rotation invariant feature detection. IEEE Trans. Circuits Syst. Video Technol. 18(12), 1703–1712 (2008)CrossRef Bonato, V., Marques, E., Constantinides, G.: A parallel hardware architecture for scale and rotation invariant feature detection. IEEE Trans. Circuits Syst. Video Technol. 18(12), 1703–1712 (2008)CrossRef
52.
Zurück zum Zitat Zhong, S., Wang, J., Yan, L., Kang, L., Cao, Z.: A real-time embedded architecture for SIFT. J. Syst. Architect. 59(1), 16–29 (2013)CrossRef Zhong, S., Wang, J., Yan, L., Kang, L., Cao, Z.: A real-time embedded architecture for SIFT. J. Syst. Architect. 59(1), 16–29 (2013)CrossRef
53.
Zurück zum Zitat Krajník, T., Šváb, J., Pedre, S., Čížek, P., Přeučil, L.: FPGA-based module for SURF extraction. Mach. Vis. Appl. 25(3), 787–800 (2014)CrossRef Krajník, T., Šváb, J., Pedre, S., Čížek, P., Přeučil, L.: FPGA-based module for SURF extraction. Mach. Vis. Appl. 25(3), 787–800 (2014)CrossRef
Metadaten
Titel
A Review of Image Interest Point Detectors: From Algorithms to FPGA Hardware Implementations
verfasst von
Cesar Torres-Huitzil
Copyright-Jahr
2016
DOI
https://doi.org/10.1007/978-3-319-28854-3_3

Premium Partner