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Erschienen in:
2003 | OriginalPaper | Buchkapitel
A Unified Framework for the Formal Verification of Sequential Circuits
verfasst von : Olivier Coudert, Jean Christophe Madre
Erschienen in: The Best of ICCAD
Verlag: Springer US
Enthalten in: Professional Book Archive
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Hardware description languages (HDLs) dramatically change the way circuit designers work. These languages can be used to describe circuits at a very high level of abstraction, which allows the designers to specify the behavior of a circuit before realizing it. The validation of these specifications is currently done by executing them, which is very costly [2]. This cost motivates the research [3, 5, 7, 10] done on the automatic verification of temporal properties of finite state machines.