20. An On-chip Router Architecture for Dependable Multicore Processor

The multicore and manycore architectures exploiting thread-level parallelism have become promising because of their high-performance and low-power consumption. However, the dependability degradation of multicore and manycore chips caused by soft errors is becoming a serious problem. In order to mitigate this problem, this chapter describes SmartCore system (smart manycore system with redundant cores and multifunction routers) to improve the dependability of a manycore chip with flexible DMR (dual modular redundancy) using redundant cores and the original NoC router named the multifunction router. We discuss the multifunction router architecture where the unique functions of the packet modification, the packet comparison to detect errors occurred on cores, and the packet duplication for DMR are realized efficiently. The benefit of the SmartCore architecture consists in its simplicity that the NoC router is capable of detecting errors as well as directing and copying the packets sent between the processor cores. This enables building manycore processor system with ease and very little overhead.