Analog IC Reliability in Nanometer CMOS

This work aims to provide the reader with a comprehensive understanding on the subject of modeling, analyzing and understanding the impact of transistor aging on analog integrated circuits (IC) in a nanometer complementary metal-oxide-semiconductor (CMOS) technology. The first chapter of this work introduces the problem studied and the major subjects addressed in this book.

For over four decades, scientists have been scaling devices to increasingly smaller feature sizes (Lewyn et al. 2009; International technology roadmap for semiconductors 2011). This trend is driven by a seemingly unending demand for ever-better performance and by fierce global competition. The steady CMOS technology downscaling is needed to meet requirements on speed, complexity, circuit density, power consumption and ultimately cost required by many advanced applications. However, going to these ultra-scaled CMOS devices also brings some drawbacks.

The focus of this work is on simulation and analysis of the impact of transistor aging on ICs integrated in nm CMOS processes. Accurate circuit simulation starts with the availability of good transistor compact models. This chapter therefore discusses the development of a set of models for simulation of the most important aging effects.

Since the introduction of the first SPICE simulator in 1973 (Nagel and Pederson 1973), circuit designers use simulators to predict and optimize circuit performance at design time. This results in huge savings in development costs and enables a designer to maximize the performance of his or her circuit in a particular technology. Over time, computer-aided design (CAD) software has become more complex and more and more aspects related to IC development have been modeled and included in circuit simulation tools. As designers try to push their designs to the limit, using technologies with ever-smaller feature sizes, more and more reliability problems pop up. Guaranteeing sufficient product yield under the presence of process variations, for example, have become one of the first major IC reliability issues. To estimate the impact of process variations at design time, EDA companies have started to offer variation-aware simulation methods such as corner simulations or Monte-Carlo (MC) simulations.

In Chap. 4, an overview of existing reliability simulators has been given. Although a lot of research has been conducted in this area, leading to the implementation of a reliability simulation framework in each of the major commercial SPICE simulators, there are still a lot of deficiencies remaining (also see Sect. 4.4). Especially with the evolution to ever-smaller CMOS devices, statistical effects resulting from process variations and stochastic aging effects become more and more important. On top of that, most academic and commercial simulators are limited to the simulation of rather small circuits. Accurate reliability evaluation of large analog or mixed-signal circuits is therefore still not possible.

IC non-idealities such as process variations and transistor aging are a potential threat for the correct operation of integrated circuits. Furthermore, aging effects become more important for circuits integrated in sub-45 nm technologies (see Chap. 2). To guarantee circuit reliability over a product’s lifetime, a foundry typically performs accelerated stress measurements on individual devices and calculates the maximum transistor operating voltages allowed in the technology process. The latter are typically defined as the stress voltage for which the drain current or threshold voltage does not exceed a given reliability margin (e.g. \({\Delta I_\mathrm{DS }}/{I_\mathrm{DS }}<10\,\%\) or \(\Delta V_\mathrm{TH }<50\) mV after \(10\) years) (also see Sect. 1.5).

In this work, the impact of transistor aging on analog circuits processed in a conventional nm CMOS process has been investigated. All important transistor aging effects have been studied and compact models for each important effect have been developed. Also, a circuit reliability simulation flow has been proposed. Finally, the flow has been applied to a set of analog circuits and the impact of aging has been studied.