Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits

The task of automatic test pattern generation for sequential circuits is to find test sequences which detect a difference between the faulty and the fault-free circuit. Since this task typically requires considerable computational resources, it provides a challenging application for parallel computer architectures.The approach proposed here considers fault parallelism, supplying every processor with a certain number of target faults, depending on the job size. Every processor does the test pattern generation and subsequent fault simulation for its faults and then returns back the generated test sequence and all target faults detected by this test sequence to a controlling process.The algorithm for partitioning the set of target faults among the number of available processors depends critically on the following three criteria: computation time, fault dependency, and job size.We implemented our approach on various computer architectures, such as an iPSC/860 HyperCube and networks of workstations (DEC and HP). All implementations use the server/client communication model.The parallel test pattern generation algorithm has been validated with the ISCAS’89 benchmark circuits, and we achieved a nearly linear speed-up.