Authentication on Presentation Layer Using Cryptographic Model for Secure Communication on FPGA Using 32-Bit Arithmetic Logic Unit and Minimized Hardware Requirement in Encryption Algorithm

Security in networking is based on cryptography, the science and art of transforming messages to make them secure and immune to attack. Cryptography can provide confidentiality, integrity, authentication of message. Cryptography can also provide entity authentication. However, cryptographic algorithms impose tremendous processing power demands that can be a bottleneck in high-speed networks. The implementation of a cryptographic algorithm must achieve high processing rate to fully utilize the available network bandwidth. To follow the variety and the rapid changes in algorithms and standards, a cryptographic implementation must also support different algorithms and be upgradeable in field. Otherwise, interoperability among different systems is prohibited and any upgrade results in excessive cost. The ultimate solution for the problem would be an adaptive processor that can provide software-like flexibility with hardware-like performance. Efficient hardware design is essentially a resource allocation problem. When the key is generated in DES, the goal is, given the constraints, to find the optimal balance between required silicon area, operation throughput, energy consumption and design time to implement a system.