Anzeige
Erschienen in:
2022 | OriginalPaper | Buchkapitel
Design and Analysis of an Integrated Class-D Power Output Stage in a 130 nm SOI-BCD Technology
verfasst von : Mustapha El Alaoui, Karim El khadiri, Ahmed Tahiri, Hassan Qjidaa
Erschienen in: WITS 2020
Verlag: Springer Singapore
Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.
Wählen Sie Textabschnitte aus um mit Künstlicher Intelligenz passenden Patente zu finden. powered by
Markieren Sie Textabschnitte, um KI-gestützt weitere passende Inhalte zu finden. powered by
Abstract
In this work, a design and analysis of an integrated class-D power output stage in 130 nm SOI-BCD technology is will be described. An output stage with two NMOS transistors is used for economize cost and area. A bootstrap circuit is important to affording the gate overdrive voltage of the NMOS transistor, especially in tall-current gate drivers with great transistors, it is mush large for integration. The proposed class-D power output stage utilizes an on-chip bootstrap circuit with integrated bootstrap capacitor. The class-D power output stage achieving a total root-mean-square (RMS) output power of 0.2 W, a THD + N (total harmonic distortion + noise) at the 8-Ω load less than 0.06%, and a power efficiency of 93%. The final design occupies approximately 1.25 mm2.