Design and Assessment of a Parallel High Performance Transport System

Applications are not able to make full use of bandwiths offered by high speed networks due to a lack of performance in current communication systems. This paper presents a parallel architecture for a front end processor (FEP) between host and high speed LAN or MAN to overcome the transport system bottleneck. The focus of the project was to demonstrate that implementation issues are of highest importance and that high performance can be achieved based on standard protocols. The FEP is designed for an OSI TP4/CLNP/LLC1 protocol stack, with an architecture general enough to be adapted to other protocols. The architecture is based on three RISC processors which are supported by special-purpose hardware for process synchronisation and for time-critical functions like checksum evaluation, buffer management and timer administration. The paper summarises design steps and features of the system. It also describes modelling and simulation and discusses main results.