Design and Characterization of an ASIC Standard Cell Library Industry–Academia Chip Collaborative Project

Standard cell design approach was important for allowing designers to scale ASICs correspondingly simple single-function ICs (of several thousand gates) to complex multi-million gate devices (SoC). Standard cell libraries are required for any IC design or chip fabrication process. The proposed work involves the design and development of an ASIC standard cell library for the 90 nm technology node using Cadence tool. The work involves identifying the optimal circuit topology for the defined logic functions, Circuit design for the functional, performance, and power dissipation specifications, Formulation of circuit simulation index for circuit characterization, design of a standard cell layout template, Layout Engineering for all the sets (DRC, LVS compliant), Parasitic Extraction and back annotation, Post layout characterization for DC, transient and power dissipation performance, and Scripting for Liberty format (Tool views). Similarly, according to our chip specifications the objective is to design optimal circuit topology like area, timing, and power.