Design and FPGA Implementation of TPFT-Based Channelization for SDR Applications

A particular channel selection can be done in wideband communication receivers that are performed by using channelization. Generally, channelization performs down conversion of signal to baseband and filtering of channel, since the features of channelization generally affected by means of software, which is much advantageous to implement channelization performance as much as possible with digital signal processing. Number of channels must be received simultaneously in base stations. Thus, each channel must contain independent channelizer, which can be achieved by Tunable Pipelined Frequency Transform (TPFT)-based channelization. So this paper deals with the design as well as the implementation of the TPFT-based channelization for any of the applications that are of software-defined radio. The coding is completed with a Verilog Hardware Description (HDL) and its simulation is completed in a Xilinx ISE 14.5 environment.