Design of a PWM/LDO Dual Mode Synchronous Buck Regulator

In order to improve some performance of the system under light load conditions, a PWM/LDO dual-mode system controlled by an external synchronous signal is presented here. In the work, we’ve designed a switching circuit based on the detailed analysis of the systematic structure and functions. The whole circuit was verified with Cadence simulations under the CSMC 0.5 μm CMOS process. The results show that when the input voltage V _in is 3.5–6 V, the output voltage V _O would be kept at 3.3 V and the operating frequency is about 1.2 MHz. In addition, the ripple of output voltage is less than 30 mV in PWM mode, while the ripple voltage is less than 10 μV and the maximum load current is up to 50 mA in LDO mode, and the converter’s overall efficiency is more than 80 %. Finally the whole circuit’s layout and post-simulation results are given. Consequently, this method can improve the overall efficiency of the system evidently.