Design of an Energy Efficient, Low Phase Noise Current-Starved VCO Using Pseudo-NMOS Logic

This paper presents the design of a current-starved VCO using pseudo-NMOS topology. The proposed design has better phase noise, lower power consumption as compared to traditional CSVCOs and the number of components are also less (8 MOSFETs are reduced). The proposed design consists of five inverter stages, and pseudo-NMOS topology is used to replace the current sourcing PMOS blocks, thereby reducing power consumption to 155.7 μW for fundamental frequency of 1.8 GHz. The simulation results depict that the proposed CSVCO has better phase noise and lower power consumption as compared to other ring VCO topologies. The circuit performance is validated in Cadence Spectre using 180 nm CMOS technology at a supply of 1.8 V. The analysis also shows that for this CSVCO, the phase noise is (−103.73 dBc/Hz) @1 MHz offset frequency and (−124.97 dBc/Hz) @10 MHz offset frequency.