Design of Ultralow Voltage-Hybrid Full Adder Circuit Using GLBB Scheme for Energy-Efficient Arithmetic Applications

In recent years, ultra low voltage (ULV) operation is gaining more importance to achieve minimum energy consumption. In this paper, the performance of the gate level body biasing (GLBB) is evaluated in subject to the subthreshold hybrid full adder logic design which employs CMOS logic and Transmission Gate (TG) logic. The performance metrics—energy, power, area, delay, and EDP are calculated and compared with the conventional CMOS (C-CMOS) Full adder. The simulations are performed in cadence at ULV of 200 mV using 90 nm CMOS technology. The obtained results showed that the proposed subthreshold hybrid full adder circuit with GLBB scheme achieves more than 44% savings in delay, 20% savings in energy consumption, and 55% savings in EDP in comparison with the conventional CMOS configuration and other hybrid counterparts.