Developing a New Generation of Reconfigurable Heterogeneous Distributed High Performance Computing System

Restrictions of current architectures of Heterogeneous High-Performance Computing (HPC) systems lead to Reconfigurable Heterogeneous HPC (RH HPC) which are able to adapt to a particular solved task on the hardware level. Highly disruptive technologies like Artificial Intelligence (AI), Internet of Things (IoT), and Machine Learning (ML) are expected to lead not only fundamental shift in classical multi-cores and multi-treads-based approaches to high-performance computing, but also open new direction in designing systems with dynamically reconfigurable runtime environment. The state-of-the-art integrated circuits allow realizing the general architecture of RH HPC at different levels of the distributed HPC: from the level of the supercomputer, to the level of user computers and the remote, built-in units intended for data acquisition, management, and control. The article describes proposed architecture for new generation of Reconfigurable Heterogeneous Distributed HPC (RHD HPC) system, including architectures of each sub-parts and highlights already developed components for such RHD HPC.