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Erschienen in:
2010 | OriginalPaper | Buchkapitel
Development of Controllability Observability Aided Combinational ATPG with Fault Reduction
verfasst von : Vaishali Dhare, Usha Mehta
Erschienen in: Recent Trends in Networks and Communications
Verlag: Springer Berlin Heidelberg
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With the increase improvement in VLSI design and progressive complication of circuits, an efficient technique for test pattern generation is necessary with the intension of reducing number of faults and with use of testability measures. Using the fault equivalence method, the number of faults are reduced. The line justification and error propagation is used to find the test vectors for reduced fault set with the aid of controllability and observability. The programs are developed for fault equivalence method, controllability observability and finally for automatic test pattern generation using object oriented language C++. ISCAS 85 C17 circuit is used for analysis purpose. Standard ISCAS (International Symposium on Circuits And Systems) netlist format is used. The stuck at fault model is considered. The complete ATPG based on controllability and observability for reduced fault set is discussed in this paper.