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Erschienen in:
1981 | OriginalPaper | Buchkapitel
Digital Signal Processing Applications of Systolic Algorithms
verfasst von : Peter R. Cappello, Kenneth Steiglitz
Erschienen in: VLSI Systems and Computations
Verlag: Springer Berlin Heidelberg
Enthalten in: Professional Book Archive
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VLSI structures and algorithms are given for bit-serial FIR filtering, IIR filtering, and convolution. We also present a bit-parallel FIR filter design. The structures are highly regular, programmable, and area-efficient. In fact, we will show that most are within log factors of asymptotic optimality. These structures are completely pipelined; that is, the throughput rate (bits/second) is independent of both word size and filter length. This is to be contrasted with algorithms designed and implemented in terms of, say, multipliers and adders whose throughput rates may depend on word length.