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2009 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Embedded Memories for Nano-Scale VLSIs

herausgegeben von: Kevin Zhang

Verlag: Springer US

Buchreihe : Integrated Circuits and Systems

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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SUCHEN

Über dieses Buch

Kevin Zhang Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications, incl- ing high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have alsobecome increasingly more complex, ranging fromstatictodynamic and volatile to nonvolatile. Among embedded memories, six-transistor (6T)-based static random access memory (SRAM) continues to play a pivotal role in nearly all VLSI systems due to its superior speed and full compatibility with logic process technology. But as the technology scaling continues, SRAM design is facing severe challenge in mainta- ing suf?cient cell stability margin under relentless area scaling. Meanwhile, rapid expansion in mobile application, including new emerging application in sensor and medical devices, requires far more aggressive voltage scaling to meet very str- gent power constraint. Many innovative circuit topologies and techniques have been extensively explored in recent years to address these challenges.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Advancement of semiconductor technology has driven the rapid growth of very large scale integrated (VLSI) systems for increasingly broad applications as shown in Fig. 1.1, including high-end and mobile computing, consumer electronics such as 3D gaming, multi-function or smart phone, and various set-top players and ubiquitous sensor and medical devices. To meet the increasing demand for higher performance and lower power consumption in many different system applications, it is often required to have a large amount of on-die or embedded memory to support the need of data bandwidth in a system. The varieties of embedded memory in a given system have also become increasingly more complex, ranging from static to dynamic and volatile to nonvolatile.
Kevin Zhang
Chapter 2. Embedded Memory Architecture for Low-Power Application Processor
Currently, the state-of-the-art high-end processors operate at 3–4 GHz frequency whereas even the fastest off-chip memory operates at just around 600 MHz [1‐6]. In decades, along with advances in processor technology, the speed gap between processors and memories has become intolerably large [7], and this speed gap has driven the processor designers to introduce a memory hierarchy into the processor architecture. For processors, it is ideal to have indefinitely large memory with no access latencies [8]. However, implementing large-capacity memory with fast operation speed is infeasible due to the physical limitations of the electrical circuits. Thus, the capacity is usually traded off with the operation speed in memory designs. For example, on-chip L1 caches are able to operate as fast as the state-of-the-art processor cores but have at most few kilobytes capacity. On the other hand, off-chip DRAMs are capable of storing few gigabytes though their operation frequencies are just around hundreds of megahertz.
Hoi Jun Yoo, Donghyun Kim
Chapter 3. Embedded SRAM Design in Nanometer-Scale Technologies
Abstract
Static random access memory (SRAM) has been embedded in almost all of VLSI chips and has played a key role in the wide variety of applications required to enhance the performances of high speed, high density, low power, low voltage, low cost, time to market. Embedded SRAM has had a long reign in upper memory hierarchy than any other memories such as dynamic random access memory (DRAM). This is largely because SRAM is able to provide the highest random access speed performance among various embedded memory technologies. In addition, SRAM is fully compatible with CMOS logic process technology and operating voltage, enabling a seamless integration with logic circuits. Meanwhile, the device miniaturization driven by the technology scaling into nanometer regime has made it more challenging to maintain a sufficient SRAM cell stability margin while continuing to increase a random access speed as the transistor threshold voltage mismatching becomes significant. This also makes it more difficult to scale the operating voltage (V DD) while keeping the compatibility with logic’s. This chapter intends to provide an overview on the state-of-the-art SRAM circuit design technologies to address the key SRAM challenges in nanometer-scale technologies in terms of the read/write stability margins, cell current, and leakages.
Hiroyuki Yamauchi
Chapter 4. Ultra Low Voltage SRAM Design
Abstract
Aggressive scaling of the supply voltage to SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in an increasing number of applications. Hence, highly energy-constrained systems, where performance requirements are secondary, benefit greatly from SRAMs that provide read and write functionality at the lowest possible voltage, particularly down to 0.3 V. However, conventional bit-cells and architectures, designed to operate at nominal supply voltages, come far short of achieving the voltage scalability required. This chapter investigates the basic degradation mechanisms in the underlying MOSFET devices, and the resulting failures modes plaguing low-voltage SRAMs. Specific solutions to manage all of these are analyzed with respect to the associated density, performance, and power trade-offs. Actual design examples are cited that achieve full read and write functionality down to 0.3 V, where the leakage-power savings can exceed a factor of 50 compared to nominal supplies.
Naveen Verma, Anantha P. Chandrakasan
5. Embedded DRAM in Nano-scale Technologies
Dynamic random access memory (DRAM) is a type of random access memory that uses charge stored on individual capacitors to hold data within an integrated circuit. Since these capacitors are non-ideal and suffer from parasitic leakages, the information eventually fades and the charge stored requires periodic refresh. Because of this refresh requirement, this memory type is classified as dynamic, in contrast to static random access memory (Fig. 5.1a) where a cross-coupled pair maintains the data state.
John Barth
Chapter 6. Embedded Flash Memory
Abstract
Chapter 6 first introduces the expanding variety of applications and requirements for embedded nonvolatile memory especially in microcontroller applications, then describes how and why embedded flash memory has expanded the functions and applications supported by process, device, and circuit technology evolutions. Embedded-specific flash memory technologies focused on the floating-gate and charge-trapping devices with split-gate and 2Tr cell concepts are overviewed in Section 6.2. Descriptions on basic embedded flash design concepts and examples of actual embedded flash designs along with challenges and future targets for embedded flash memory are provided in Section 6.3.
Hideto Hidaka
Chapter 7. Embedded Magnetic RAM
Abstract
In Chapter 7, magnetic RAM (MRAM) technology is introduced as a key technology candidate for creating new applications such as nonvolatile RAM. After an introduction of the history and basic principles of MRAM, we look into MRAM technology and basic design as well as on various memory cell architectures in Section 7.1. Then overviews on representative MRAM design examples, possible applications, and future challenges of MRAM are provided in Section 7.2. Finally nonvolatile memory frontiers and challenges are discussed in Section 7.3 as a conclusion of Chapters 6 and 7. The focus of this chapter is to highlight and summarize important concepts of the new technology.
Hideto Hidaka
Chapter 8. FeRAM
Ferroelectric materials show spontaneous polarization; FeRAM utilizes the positive and negative polarization direction corresponding to “1” and “0” states for stored data. The basic idea behind FeRAM appeared in 1963 [1] and 1988 [2], however, there have been many scientific and technical improvements needed to convert FeRAM technology into manufactured devices and still further improvements in materials, process fabrication, and circuit architecture are required for further device scaling. This chapter intends to serve as a review primarily focusing on the timeframe from 2000 to 2007. Previously, circuit and architecture of FeRAM devices regarding circuit innovations up to 2000 was summarized by Prof.
Shoichiro Kawashima, Jeffrey S. Cross
Chapter 9. Statistical Blockade: Estimating Rare Event Statistics for Memories
Abstract
As we move deeper into sub-65 nm technology nodes, uncontrollable random parametric variations have become a critical hurdle for achieving high yield. This problem is particularly crippling for high-replication circuits (HRCs) – circuits like SRAM cells, nonvolatile memory cells, and other memory cells that are replicated millions of times on the same chip – because of aggressive cell design, the requirement of meeting very high >5σ levels of yield and the usual higher sensitivity of such circuits to process variations. However, it has proved difficult to even estimate such high yield values efficiently, making it very difficult for designers to adopt an accurate, variation-aware design methodology. This chapter develops a general statistical methodology to estimate parametric memory yields. The keystone of the methodology is a technique is called statistical blockade, which combines Monte Carlo simulation, machine learning, and extreme value theory to simulate very rare failure events and to compute analytical models for the tail distributions of the circuit performance metrics. Several circuit examples are analyzed in detail to enable a deep understanding of the theory and its practical use in a real-world setting. The treatment is directed toward both the memory designer and the EDA engineer.
Amith Singhee, Rob A. Rutenbar
Backmatter
Metadaten
Titel
Embedded Memories for Nano-Scale VLSIs
herausgegeben von
Kevin Zhang
Copyright-Jahr
2009
Verlag
Springer US
Electronic ISBN
978-0-387-88497-4
Print ISBN
978-0-387-88496-7
DOI
https://doi.org/10.1007/978-0-387-88497-4

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