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Erschienen in:
2014 | OriginalPaper | Buchkapitel
Evaluation of ASIC Implementation of Physical Random Number Generators Using RS Latches
verfasst von : Hirotaka Kokubo, Dai Yamamoto, Masahiko Takenaka, Kouichi Itoh, Naoya Torii
Erschienen in: Smart Card Research and Advanced Applications
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Abstract
Embedded devices such as smart cards and smart phones are used for secure systems, for example automated banking machines and electronic money. The security of an embedded device depends strongly on secret information; cryptographic keys, nonces for authentication or seeds for a pseudo random number generator, which is generated by a Physical True Random Number Generator (PTRNG). If a PTRNG generates random numbers with a low entropy, the security of the embedded device has a vulnerability because secret information may be predictable by attackers due to the low entropy. Hence PTRNGs are required to provide high-quality physical random numbers even in an undesirable environment, that is, low/high temperature or supply voltage. PTRNGs also must be small-scale and consume low power due to the limited hardware resources in embedded devices.
In this paper, we fabricate and evaluate 39 PTRNGs using RS Latches on 0.18\(\,\upmu \) m ASICs. Physical random numbers were generated from the exclusive-OR of 256 RS latches’ outputs. Our PTRNGs passed the SP800-90B Health Tests and the AIS31 Tests while changing both temperature (from \(-20\,^\circ \mathrm{C}\) to \(60\,^\circ \)C) and voltage (1.80 V \(\,\pm 10\,\%\)), and thus, we were able to confirm that our PTRNGs have high-robustness against environmental stress. The power consumption and circuit scale of our PTRNG are 0.27 mW and 984.5 gates, respectively. Our PTRNG using RS latches is small enough to be implemented on embedded devices.