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Erschienen in:
Introduction to Energy-Efficient Fault-Tolerant Systems Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

6. Fault-Tolerant Reconfigurable On-Chip-Network

verfasst von : Mohammad Hosseinabady, Jose L. Nunez-Yanez

Erschienen in: Energy-Efficient Fault-Tolerant Systems

Verlag: Springer New York

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Abstract

Fault-tolerant reconfigurable on-chip networks are infrastructure communication architectures for the future computing platforms that can run many applications with dynamic work-load in the presence of different types of faults in the system. This chapter introduces the architecture of such platforms and studies their fault-tolerant features.

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Vorheriges Kapitel System-Level Design Methodology
Nächstes Kapitel Bio-Inspired Online Fault Detection in NoC Interconnect
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Metadaten
Titel
Fault-Tolerant Reconfigurable On-Chip-Network
verfasst von
Mohammad Hosseinabady
Jose L. Nunez-Yanez
Copyright-Jahr
2014
Verlag
Springer New York
Buch
Energy-Efficient Fault-Tolerant Systems

Print ISBN: 978-1-4614-4192-2

Electronic ISBN: 978-1-4614-4193-9

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-1-4614-4193-9_6

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