Fixed-Point High-Speed Parallel Multipliers in VLSI

The paper presents techniques to increase the speed of fixed-point parallel multipliers and reduce the multiplier chip size for VLSI realizations. It is shown that a higher order (octal) version of the Booth’s Algorithm will lead to significant improvements in speed, coupled with a decrease of chip area and power consumption, as compared to the modified (quaternary) version of the Booth’s Algorithm presently used in or proposed for monolithic multipliers. In addition, further speed improvements can be obtained by using Wallace trees or optimal Dadda types of realizations.The optimal Dadda realizations with minimal number of adders can be layed out in a regular, rectangular array interleaved with partial product generation. The resulting regular structure is suitable for VLSI implementations. The more complex interconnection wiring which is needed is shown to be feasable in technologies with at least 3 layers of interconnections. Layout, interconnection and speed considerations for the proposed high-speed VLSI parallel multiplier configurations have been studied.