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This book discusses non-conventional digital signal processing based on direct processing of delta-sigma modulated bit-stream. The main attributes of low-pass delta-sigma analog-to-digital converters are: simple and inexpensive design, robustness of design to component tolerances, low-power consumption, high input impedance, high resolution (more than 20 bits) and possibility of direct arithmetic operation on its bit-stream. The author presents a number of theoretical and simulation results related to newly proposed linear and non-linear circuits such as delta-sigma adders, delta-sigma rectifiers, delta-sigma RMS and AGC circuits, delta-sigma frequency deviation meters, etc. The proposed circuits are not application limited and can be used in instrumentation, sensor application, bio-medical application, communications, etc.

Presents novel linear and nonlinear circuits for direct processing of delta-sigma modulated bit-stream;The proposed circuits are supported by theoretical and simulation results;Recommends potential applications of the proposed circuits, and proposes ideas for further investigation.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Basics of Low-Pass Delta Modulation

Abstract
Multi-bit analog-to-digital converters (ADC) have dominated digital signal processing (DSP) for the last 50 years or so. There are many ADC conventional architectures such as successive approximation register (SAR) ADC, flash ADCs, integrating, ramp-compare, Wilkinson, and others. All operate at a Nyquist sampling rate fN. Since the Nyquist rate ADC converters operate at sampling frequency fN, which is approximately two times the maximum frequency of input signal (fN > = 2fmax = 2fB), a high-order low-pass filter (LPF) is required to limit higher frequency components than fmax = fB of an input signal entering ADC. This filter is usually referred to as an anti-aliasing filter (AAF). This is a higher-order analog filter, and it is more expensive than an entire ADC. To overcome problems of an anti-aliasing filter and complexity of an n-bit ADC, linear delta modulation (LΔM) was proposed [1]. It trades off amplitude quantization of n-bit ADC for 1-bit quantization using oversampling technique. Primary use of highly oversampled LΔM is in a LΔM-to-PCM conversion. To improve signal-to-noise ratio and dynamic range, higher-order LΔM was proposed [2]. Unfortunately, LΔM systems have problems related to stability, slope overload, and accumulation of errors during transmission. To overcome these problems, Inose and Yasuda proposed an improved method of a one-bit analog-to-digital conversion of low-frequency analog signals. The paper of Inose and Yasuda can be found in the edited book of Candy and Temes [3]. Their proposed method is known as delta-sigma modulation (Δ-ΣM). This inexpensive, low-power consuming, high-resolution ADC revolutionized VLSI System-on-Chips (SoCs) design. In 1989, Schrier and Snelgrove [4] extended oversampling and noise principles of low-pass Δ-ΣM to applications at intermediate and radio frequencies (IF and RF). This method of ADC conversion is known as band-pass delta-sigma modulation (BP Δ-ΣM) [1013]. Because LP Δ-ΣM plays a very important role in many applications, such as sensor networks, hand-held mobile devices (cellular phone, GPS, etc.), wireless networks, software-defined radio, etc., we will briefly describe the principles of its operations. Both techniques are based on principles of oversampling and noise shaping. Both techniques trade off amplitude quantization of n-bit ADCs for oversampling of one-bit ADCs. This trade-off is possible under the condition of meeting a certain signal-to-noise ratio (SNR) for a specific dynamic range. In the following section, we will briefly describe operation of low-pass (LP) delta modulation.
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Chapter 2. Linear Processing of a Delta-Modulated Bit-Stream

Abstract
In the last four decades modest progress has been made in the area of direct processing of a delta-modulated stream. High resolution, simplicity, and the low cost of a delta modulation encoder have been the main reasons for using this encoder in digital signal processing. Traditionally delta modulation encoded filtering is achieved by means of Nyquist rate decimators. To avoid the process of rate conversion and decimation filtering, a number of authors recommended direct processing of delta modulation pulse stream in general, and in particular a Δ-Σ modulation bit-stream. However, because of the high oversampling rate of a Δ-Σ bit-stream, specific arithmetic circuits such as a delta adder, multiplier, etc. must be developed. Here in brief, we will mention some of the most relevant works related to linear processing of delta-modulated bit-stream.
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Chapter 3. Rectification of a Delta-Sigma Modulated Signal

Abstract
Techniques of direct processing of the Δ-Σ modulated pulse stream emerged more than four decades ago. In 1978, N. Kouvaras [1] proposed the use of a serial binary adder as a delta adder, with an interchanged role of the Sum and Carry—out terminals of the binary adder. In that paper, Kouvaras defined the formula to find the sum of two Δ-Σ modulated pulse streams and used a delta adder as a basic processing element in the implementation of FIR and IIR filters. Over the years, a number of papers have been published dealing with linear processing of Δ-Σ modulated pulse streams [2–4]. Analytical evaluation and proof of Kouvaras’ formulas were elaborated in Chap. 2.
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Chapter 4. Multiplication of Two ∆-Σ Bit-Streams

Abstract
In spite of the fast progress of semiconductor technology, there are still a number of open problems with n-bit digital signal processing (DSP). For example, flash analog-to-digital converters are bulky and power hungry. Digital multiplying circuits are bulky and power hungry as well. This problem becomes more acute when we deal with applications which require a 20-bit or more resolution. Length of the code word can be efficiently reduced by using a differential pulse-code modulation (DPCM). ∆-ΣM is a one-bit DPCM system and employs a trade-off between a number of amplitude quantization levels and sampling frequency.
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Chapter 5. Digital Architecture for Delta-Sigma RMS-to-DC Converter

Abstract
Δ-Σ modulation is a well-established analog-to-digital conversion (ADC) process. It is a low-power consuming, high-resolution, one-bit conversion process, and it is suitable for VLSI design. It has applications in low-frequency ADC processes such as biomedical applications, environmental monitoring, seismic, instrumentation, etc. It also has applications in audio and radio frequencies. The RMS-to-DC Δ-ΣM circuit can be used for automatic-gain control (AGC) of the amplifier to maintain a constant output level of varying waveform. The RMS-to-DC Δ-ΣM instrument can be used as a low-cost true RMS digital panel meter for direct measurement of power consumption in different household appliances such as stoves, TV sets, refrigerators, etc. It can be implemented as an AC line-powered version. The RMS-to-DC Δ-ΣM circuit can be used as a portable, high-impedance input RMS panel meter and dB meter for a modem line monitor. The RMS-to-DC Δ-ΣM can be used in micro-grid power lines metering and mobile communication radio frequency level monitoring. In addition, RMS-to-DC Δ-ΣM circuit has applications in data acquisition systems for detection of a signal level, or testing and grading components such as transistors, op amplifiers, and many others.
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Chapter 6. Companding Circuits and Systems Based on Δ-Σ Modulation

Abstract
There are several publications and patents dealing with companding of analog signals. Most of these publications deal with analog implementation of companding circuits, which are used in telephone transmission systems. In the past six decades, pulse-code modulation (PCM) was used as an analog-to-digital converter (ADC) in digital telephone systems. The PCM encoding schemes are recommended by the International Telecommunication Union (ITU) and are the international PCM companding standards. European countries practice logarithmic A-Law, while logarithmic μ-law companding technique is used in North America and Japan. A brief introduction about the need for companding in PCM-based digital telephone systems can be found in references [1–3]. In addition, there are a number of communication books describing in detail the operation of PCM technique [4]. Existing compander systems are composed of complex analog circuits that provide good sound quality. However, analog circuits are, by their nature, subject to variable performance, and use of advanced techniques is required to keep performance levels constant. There are compander integrated circuit (IC) chips on the market [5, 6]. Their implementation is analog in nature.
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Chapter 7. A Δ-Σ Digital Stereo Multiplexing–Demultiplexing System

Abstract
Frequency modulation (FM) stereo broadcasting technique is well understood in literature and practice and is regulated by federal law (FCC). This stereo broadcast is not limited to FM; the FCC has authorized some form of stereo AM broadcast as well. There are a number of books and references describing the FM stereo technique. In Fig. 7.1 a generic block diagram of a stereo FM system is shown [1]. Similar block diagrams of a stereo FM system can be found in many other references and on the Internet. Thus, following general notation in this figure, we will briefly describe the operation of the system and point out its disadvantages. The idea of stereo is to provide a sound wave-front which replicates the depth and realism that an individual experiences when listening. As can be seen in Fig. 7.1, the signal broadcast consists of two channels: left (L) and right (R). This signal can be derived from a microphone, tape, or CD player, or another source. In the case of a broadcast of speech or music, the frequency bandwidth is from 30 Hz to 15 kHz. With FM stereophonic broadcasting, voice or music channels are frequency division multiplexed onto a single FM carrier. The L and R audio channels are combined in analog adder networks to produce the (L − R) and (L + R) audio channels. As one can see, the (L + R) signal is used to modulate the carrier just as a non-stereo signal does. The (L − R) signal is shifted by a balance modulator (subcarrier frequency is 38 kHz) to produce a double sideband (DSB) suppressed carrier (SC) signal spanning 38 − 15 = 23 kHz and 38 + 15 = 53 kHz. This process of stereo multiplexing is known as MPX. For demodulation purposes (synchronization), a 19 kHz pilot signal is also transmitted. All three signals are combined and delivered to an FM radio frequency transmitter. Most FM transmitters now use an integrated circuit (IC). Motorola MC1376 IC is a complete FM modulator. Unfortunately, it requires several external analog components to make it operate (including two inductor (coil) components). Similarly, the XR-1310 stereo demodulator has a significant number of analog components. Thus, FM IC chips have to be buffered by a number of analog components, which it is not possible to integrate. There are several US Patents proposing different digital stereo methods, but they are not related to the digital stereo multiplexing–demultiplexing method we are proposing.
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Chapter 8. A Δ-Σ Digital Amplitude Modulation System

Abstract
Amplitude modulation (AM) is a very well understood and developed signal processing technique. AM was the earliest modulation method used to transmit voice by radio. It was developed during the first quarter of the twentieth century. There are numerous publications on this subject, including scientific papers, books, patents, and IC data sheets. Basic principles of its operation can be found on the Internet or in any communications textbook [1, 2]. In addition to the classic analog amplitude modulation, there are several digital amplitude modulation techniques. The oldest one is on-off keying (OOK) which dates to the time of Morse telegraph transmission. Still today, many wireless sensors working at 433 MHz use OOK. Over the years various modulation techniques have been developed such as pulse amplitude modulation (PAM), m-ary PAM, amplitude shift keying (ASK) [2], etc. Use of the Δ-Σ modulation for RF applications is elaborated in reference [3]. It is worth mentioning that a Δ-Σ modulation is frequently referred to as a pulse density modulation [3, 4] because the density of pulses of a Δ-Σ pulse stream is proportional to the amplitude of an input signal. The proposed UC Berkeley RF pulse density system generates an amplitude-modulated waveform with up to 20 MHz envelope bandwidth and demonstrates the validity of this approach for modern communication standards [3].
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Chapter 9. Δ-Σ Methods for Frequency Deviation Measurement of a Known Nominal Frequency Value

Abstract
Telecommunication and electric power systems are the two manmade dynamic systems. Reliability of these systems is of great importance to the security and economic well-being of modern society. These systems extend over thousands of kilometers, and their protection and stable operation require enormous investment. To ensure stable and reliable operations many system parameters have to be monitored. One of the most important parameters in power systems is the frequency. Frequency variation can affect system operation considerably. In power systems the supply and demand must be in balance. The frequency of the power source is related to the current drawn by different loads of the grid. Both effects, overload and underload, are undesirable. Thus, it is very important that the frequency of a power system is maintained very close to its nominal frequency. There are several methods proposed in the past for frequency deviation monitoring in power systems. In reference [1] the authors proposed a frequency computation technique suitable for single- or three-phase voltage signals. This method uses a level crossing detector which yields several estimates of the frequency within one cycle. In reference [2], the authors proposed a method for the precise measurement of the difference between two low frequencies. The method is based on multiplying the two incoming frequencies by a large factor. They offer a simple and inexpensive solution for a frequency difference meter. The authors of reference [3] offer three novel techniques for frequency measurement in power networks in the presence of harmonics. All three algorithms—zero crossing, DFT method, and phase-demodulation methods—were tested and verified by simulations. A relatively simple method for measuring and display of the line frequency deviation from its nominal value is proposed in reference [4]. This counting method is based on multiplication of the reference and measured signals. The zero-crossing technique for the purpose of frequency determination of a power signal is presented in reference [5]. The Fourier algorithm is used for digital filtering. The verification of the proposed algorithm is done using a DAQ device in conjunction with LabVIEW. S. J. Arif [6] proposed the use of a zero-crossing detector to produce a pulse train which is combined digitally with a clock of 10 KHz and then passed through a decade counter to give the unique contribution of pulses which are encoded and displayed. This method offers a resolution of 0.5 Hz. The use of a two-arm bridge for frequency deviation measurement is proposed in reference [7]. It is an analog implementation, which uses the principle of orthogonality. This system is sensitive to input amplitude variation and additive noise as well. The use of the two-arm bridge, based on the use of Δ-Σ modulation, is proposed in reference [8]. Orthogonality is based on the use of an analog integrator. Thus, this system is sensitive to input amplitude variation. A DSP technique is proposed in reference [9]. It uses a microcomputer and data acquisition card. It offers an accurate estimate of the order of 0.02 Hz for nominal, near-nominal, and off-nominal frequencies. A ROM-based frequency deviation meter is proposed in reference [10]. It consists of two look-up tables and complex timing and control circuits. It offers near 1 mHz resolution for indoor installation with near constant temperature. The experimental circuit discussed in [11] uses PLL for multiplication of 50 or 60 Hz frequencies by 100. It has a resolution of 0.01 Hz. A programmable frequency meter for low frequencies with known nominal value is proposed in [12]. The percentage of error is 0.174% for 50 Hz. A flexible programmable circuit for generation of a radio frequency signal for transmission is proposed in US Patent No: 2006/011595 A1. This digital modulation scheme uses the well-known principle of carrier orthogonality. It is known in theory and practice as a quadrature modulation. A proposed delta-sigma transmitter consists of a quadrature digital clock generator, two delta modulators, a pair of commutators (multipliers), analog summing amplifier, band-pass filter (BPF), and antenna. Input to the system is N-bit digital word generated by a controller (micro-processor). One-bit commutator is implemented using exclusive OR (XOR) gate. The quadrature clock generator is implemented using master–slave “D” flip-flop (or a four-stage ring oscillator). A 90-degree phase difference needs only to be approximately 90-degrees. A clock frequency of a phase generator must be greater than 1 MHz (even order of GHz) to shift an information in desired radio frequency bandwidth. A transmitted signal is arbitrary, and knowledge of frequency of a source is not required. Thus, this invention is meant for the transmission of information, not for instrumentation, i.e., detection of deviation of a known nominal frequency value. The first essential component for linear processing of a Δ-Σ bit-stream is a delta adder (DA) proposed by Kouvaras [13]. A DA adder is, in fact, a binary adder with interchanged roles of sum and carry-out terminals. The second vital component, used in this chapter, is a rectifying encoder (RE) [14], which can serve as a squaring circuit operator as well [15] [US Patent 9,141,339 B2]. Implementation of the proposed methods is based on the addition and squaring operation on an orthogonal Δ-Σ modulated bit-stream. Thus, operation of these circuits is based on linear and nonlinear operations on orthogonal Δ-Σ bit-streams, in order to detect violation of the orthogonality law when a signal of known nominal frequency value changes.
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Chapter 10. Δ-Σ Automatic-Gain Controller

Abstract
Automatic-gain control (AGC) is a closed-loop feedback regulating circuit. It is used in many systems to maintain a nearly constant signal amplitude at its output despite variation of the signal amplitude at the input. Its role is to reduce the amplitude dynamic range so that circuits following the AGC can handle a reduced dynamic range. In 1925, Harold A. Wheeler invented and patented automatic volume control (AVC). Karl Küpfmüller published an analysis of AGC systems in 1928. By the early 1930s most new commercial broadcast receivers included AVC [1]. AM radio has used AGC since then. It is used in most radio receivers to equalize the average volume (loudness) of different radio stations due to differences in the received signal strength, as well as variations in a single station's radio signal due to fading. Related applications of AGC are in radar systems, telephone recording, audio/video recording, biological sensory systems, etc. Correct operation of mobile telephone systems is greatly dependent on AGC due to environmental factors such as seasonal change in vegetation, fluctuation of users, overpower of a neighboring base station, etc. A block diagram of a typical AGC is shown in Fig. 10.1. In brief, we will describe its operation as presented in [2]. As can be seen, the output of VGA, signal V1, is fed back to the detector of the amplitude change and to the next device in the signal-processing chain as well. If needed, signal V1 can be amplified. A detector block can be implemented as an envelope (or rectifier), square law, true RMS, or logarithmic. A detected signal V2 is smoothed (low-pass filtered) to produce a nearly DC signal. This signal is compared with a reference signal VR. The result of the comparison is used to generate the control voltage Vc to adjust the gain of the VGA. There are many publications, books, patents, VGA circuit solutions, and Internet sites dealing with theory, implementation, and applications of AGC devices. There are IC chips on the market as well. For instance, Analog Devices Inc. application note describes a low-frequency AGC circuit (AD8336) used in audio and power equipment [3]. A block diagram of a delta-sigma based automatic-gain control circuit is presented in reference [4]. However, rectification of analog input signal is done off delta-sigma IC chip, with the use of analog components.
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Chapter 11. Δ-Σ Integrator and Differentiator

Abstract
Digital integrators and differentiators are an integral part of many systems like control, communications, audio, medical, and DSP in general. Both digital integrators and differentiators can be classified as finite impulse response (FIR) or infinite impulse response (IIR) filters. IIR digital solutions are preferred because their implementation is simpler, and they have much better magnitude response. However, their phase characteristics are not linear in comparison with FIR filters, which can cause problems in some applications. The frequency response of an ideal integrator is
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