High Level Verification of I²C Protocol Using System Verilog and UVM

Present-day technology has reached a goal where an entire system can be implemented on a single chip which is nothing but called system on chip (SOC). It involves microcontrollers and various peripheral devices with each peripheral device having its own intellectual property (IP) named as IP cores. Serial communication is established between these IP cores using various protocols like RS232, RS422 and UART etc. They perform point to point communication which requires huge wiring connections, multiplexing of all the bus connections to deliver the information to the IP Cores. To overcome this I²C protocol is developed by Philips, which is a two line communication. Here only two pins, i.e., SCL and SDA establish connection between various devices considering one as master and other as slave (Eswari et al. in Implementation of I²C Master Bus Controller on FPGA, 2013) [1]. These two pins communicate using particular commands like start, address, read/write, acknowledgement and stop commands. These commands show a particular format in which data should transfer. Both 7-bit and 10-bit addressing formats can be used, 10-bit addressing supports more addressing lines, i.e., 1024 compared to 127 addressing lines in 7-bit mode. The advantage in this protocol is it has low wiring data transfer rate that can be improved using Ultra-Fast mode (UFm) (Bandopadhyay in Designing with Xilinx FPGAs. Springer, Switzerland, 2017) [2]. Ultra-Fast mode is a unidirectional data transfer mode, i.e., only writing data to an address can be done. In this paper they perform verification for the design of an I²C protocol between a master and a slave using system Verilog and UVM in the tool SimVision.