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2017 | OriginalPaper | Buchkapitel

13. In-Memory Data Compression Using ReRAMs

verfasst von : Debjyoti Bhattacharjee, Anupam Chattopadhyay

Erschienen in: Emerging Technology and Architecture for Big-data Analytics

Verlag: Springer International Publishing

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Abstract

Data compression is a key building block in the current age of information deluge. It is necessary for efficient storage management, effective utilization of communication bandwidth and eventually helps to refine the data to provide information and knowledge. Given the growth of sensors and connected devices, the role of compression in data management is growing in importance steadily. Following the earliest computing abstractions, data is transferred between storage and computing blocks. Any form of processing, including the compression, needs to be run in the computing segment, and returned back to the storage. This basic notion is challenged by the advent of several new technologies, which support logic operations and storage on the same device. Consequently, in-memory computing platforms are being studied by researchers and commercial entities for their applicability in different scenarios, such as data encryption and on-chip machine learning. This chapter explores the implementation of data compression algorithm using such an in-memory computing platform. We explain the building blocks of the in-memory computing architecture, the steps of a data compression algorithm and show step-by-step the mapping process.

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Literatur
1.
Zurück zum Zitat R. Waser, R. Dittmann, G. Staikov, K. Szot, Redox-based resistive switching memories–nanoionic mechanisms, prospects, and challenges. Adv. Mater. 21, 2632–2663 (2009)CrossRef R. Waser, R. Dittmann, G. Staikov, K. Szot, Redox-based resistive switching memories–nanoionic mechanisms, prospects, and challenges. Adv. Mater. 21, 2632–2663 (2009)CrossRef
2.
Zurück zum Zitat E. Linn, R. Rosezin, C. Kügeler, R. Waser, Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9 (5), 403–406 (2010)CrossRef E. Linn, R. Rosezin, C. Kügeler, R. Waser, Complementary resistive switches for passive nanocrossbar memories. Nat. Mater. 9 (5), 403–406 (2010)CrossRef
3.
Zurück zum Zitat J. Ziv, A. Lempel, A universal algorithm for sequential data compression. IEEE Trans. Inf. Theory 23 (3), 337–343 (1977) J. Ziv, A. Lempel, A universal algorithm for sequential data compression. IEEE Trans. Inf. Theory 23 (3), 337–343 (1977)
4.
Zurück zum Zitat D. Bhattacharjee, R. Devadoss, A. Chattopadhyay, ReVAMP: ReRAM based VLIW Architecture for in-Memory comPuting, in Design, Automation & Test in Europe Conference & Exhibition, DATE 2017 (2017) D. Bhattacharjee, R. Devadoss, A. Chattopadhyay, ReVAMP: ReRAM based VLIW Architecture for in-Memory comPuting, in Design, Automation & Test in Europe Conference & Exhibition, DATE 2017 (2017)
5.
Zurück zum Zitat A. Siemon, S. Menzel, A. Marchewka, Y. Nishi, R. Waser, E. Linn, Simulation of TaO x -based complementary resistive switches by a physics-based memristive model, in Circuits and Systems ISCAS (2014, IEEE International Symposium on), pp. 1420–1423 A. Siemon, S. Menzel, A. Marchewka, Y. Nishi, R. Waser, E. Linn, Simulation of TaO x -based complementary resistive switches by a physics-based memristive model, in Circuits and Systems ISCAS (2014, IEEE International Symposium on), pp. 1420–1423
6.
Zurück zum Zitat E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, R. Waser, Beyond von neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23 (30), 305205 (2012) E. Linn, R. Rosezin, S. Tappertzhofen, U. Böttger, R. Waser, Beyond von neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology 23 (30), 305205 (2012)
7.
Zurück zum Zitat Emerging Research Devices (ERD) report, International Technology Roadmap for Semiconductors (ITRS) (2013) Emerging Research Devices (ERD) report, International Technology Roadmap for Semiconductors (ITRS) (2013)
8.
Zurück zum Zitat J. Borghetti, G.S. Snider, P.J. Kuekes, J. Joshua Yang, D.R. Stewart, R. Stanley Williams, ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464 (7290), 873–876 (2010) J. Borghetti, G.S. Snider, P.J. Kuekes, J. Joshua Yang, D.R. Stewart, R. Stanley Williams, ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464 (7290), 873–876 (2010)
9.
Zurück zum Zitat E. Lehtonen, M. Laiho, Stateful implication logic with memristors, in Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures (2009), pp. 33–36 E. Lehtonen, M. Laiho, Stateful implication logic with memristors, in Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures (2009), pp. 33–36
10.
Zurück zum Zitat S. Kvatinsky, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Memristor-based material implication (imply) logic: design principles and methodologies. IEEE TVLSI 22 (10), 2054–2066 (2014) S. Kvatinsky, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Memristor-based material implication (imply) logic: design principles and methodologies. IEEE TVLSI 22 (10), 2054–2066 (2014)
11.
Zurück zum Zitat A. Siemon, S. Menzel, R. Waser, E. Linn, A complementary resistive switch-based crossbar array adder. IEEE JETCAS 5 (1), 64–74 (2015) A. Siemon, S. Menzel, R. Waser, E. Linn, A complementary resistive switch-based crossbar array adder. IEEE JETCAS 5 (1), 64–74 (2015)
12.
Zurück zum Zitat D. Bhattacharjee, F. Merchant, A. Chattopadhyay, Enabling in-memory computation of binary blas using reram crossbar arrays, in 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016, pp. 1–6 D. Bhattacharjee, F. Merchant, A. Chattopadhyay, Enabling in-memory computation of binary blas using reram crossbar arrays, in 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016, pp. 1–6
13.
Zurück zum Zitat D. Bhattacharjee, A. Chattopadhyay, Efficient binary basic linear algebra operations on reram crossbar arrays, in 2017 30th International Conference on VLSI Design, January 2017 D. Bhattacharjee, A. Chattopadhyay, Efficient binary basic linear algebra operations on reram crossbar arrays, in 2017 30th International Conference on VLSI Design, January 2017
14.
Zurück zum Zitat D.B. Strukov, D.R. Stewart, J. Borghetti, X. Li, M. Pickett, G.M. Ribeiro, W. Robinett, G. Snider, J. P. Strachan, W. Wu, Q. Xia, J.J. Yang, R.S. Williams, Hybrid cmos/memristor circuits, in ISCAS, pp. 1967–1970 (2010) D.B. Strukov, D.R. Stewart, J. Borghetti, X. Li, M. Pickett, G.M. Ribeiro, W. Robinett, G. Snider, J. P. Strachan, W. Wu, Q. Xia, J.J. Yang, R.S. Williams, Hybrid cmos/memristor circuits, in ISCAS, pp. 1967–1970 (2010)
15.
Zurück zum Zitat K.-H. Kim, S. Gaba, D. Wheeler, J. M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/cmos system for data storage and neuromorphic applications. Nano Letters 12 (1), 389–395 (2011)CrossRef K.-H. Kim, S. Gaba, D. Wheeler, J. M. Cruz-Albrecht, T. Hussain, N. Srinivasa, W. Lu, A functional hybrid memristor crossbar-array/cmos system for data storage and neuromorphic applications. Nano Letters 12 (1), 389–395 (2011)CrossRef
16.
Zurück zum Zitat M.P. Sah, H. Kim, L.O. Chua, Brains are made of memristors. IEEE Circuits Syst. Mag. 14 (1), 12–36 (2014)CrossRef M.P. Sah, H. Kim, L.O. Chua, Brains are made of memristors. IEEE Circuits Syst. Mag. 14 (1), 12–36 (2014)CrossRef
17.
Zurück zum Zitat L. Ni, Y. Wang, H. Yu, W. Yang, C. Weng, J. Zhao, An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar, in ASP-DAC, January 2016, pp. 280–285 L. Ni, Y. Wang, H. Yu, W. Yang, C. Weng, J. Zhao, An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar, in ASP-DAC, January 2016, pp. 280–285
18.
Zurück zum Zitat F. Alibart, T. Sherwood, D.B. Strukov, Hybrid cmos/nanodevice circuits for high throughput pattern matching applications, in Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on (2011), pp. 279–286 F. Alibart, T. Sherwood, D.B. Strukov, Hybrid cmos/nanodevice circuits for high throughput pattern matching applications, in Adaptive Hardware and Systems (AHS), 2011 NASA/ESA Conference on (2011), pp. 279–286
19.
Zurück zum Zitat S. Hamdioui, L. Xie, H. Anh Du Nguyen, M. Taouil, K. Bertels, H. Corporaal, H. Jiao, F. Catthoor, D. Wouters, L. Eike, J. van Lunteren, Memristor based computation-in-memory architecture for data-intensive applications, in Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, March 9–13, 2015 (2015), pp. 1718–1725 S. Hamdioui, L. Xie, H. Anh Du Nguyen, M. Taouil, K. Bertels, H. Corporaal, H. Jiao, F. Catthoor, D. Wouters, L. Eike, J. van Lunteren, Memristor based computation-in-memory architecture for data-intensive applications, in Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, March 9–13, 2015 (2015), pp. 1718–1725
20.
Zurück zum Zitat P.-E. Gaillardon, L. Amaru, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, The Programmable Logic-in-Memory (PLiM) computer, in DATE (2016), pp. 427–432 P.-E. Gaillardon, L. Amaru, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, The Programmable Logic-in-Memory (PLiM) computer, in DATE (2016), pp. 427–432
21.
Zurück zum Zitat J.H. Poikonen, E. Lehtonen, M. Laiho, On synthesis of Boolean expressions for memristive devices using sequential implication logic. IEEE TCAD 31 (7), 1129–1134 (2012) J.H. Poikonen, E. Lehtonen, M. Laiho, On synthesis of Boolean expressions for memristive devices using sequential implication logic. IEEE TCAD 31 (7), 1129–1134 (2012)
22.
Zurück zum Zitat A. Raghuvanshi, M. Perkowski, Logic synthesis and a generalized notation for memristor-realized material implication gates, in ICCAD (2014), pp. 470–477 A. Raghuvanshi, M. Perkowski, Logic synthesis and a generalized notation for memristor-realized material implication gates, in ICCAD (2014), pp. 470–477
23.
Zurück zum Zitat A. Chattopadhyay, Z. Endre Rakosi, Combinational logic synthesis for material implication, in IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong (2011), pp. 200–203 A. Chattopadhyay, Z. Endre Rakosi, Combinational logic synthesis for material implication, in IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong (2011), pp. 200–203
24.
Zurück zum Zitat M. Soeken, S. Shririnzadeh, P.-E. Gaillardon, L. Amarú, R. Drechsler, G. De Micheli, An mig-based compiler for programmable logic-in-memory architectures, in DAC (2016) M. Soeken, S. Shririnzadeh, P.-E. Gaillardon, L. Amarú, R. Drechsler, G. De Micheli, An mig-based compiler for programmable logic-in-memory architectures, in DAC (2016)
25.
Zurück zum Zitat S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs, in DATE (2016) S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs, in DATE (2016)
26.
Zurück zum Zitat L. Xie, H. Anh Du Nguyen, M. Taouil, K. Bertels, S. Hamdioui, Fast boolean logic mapped on memristor crossbar, in 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, October 18–21 (2015), pp. 335–342 L. Xie, H. Anh Du Nguyen, M. Taouil, K. Bertels, S. Hamdioui, Fast boolean logic mapped on memristor crossbar, in 33rd IEEE International Conference on Computer Design, ICCD 2015, New York City, NY, October 18–21 (2015), pp. 335–342
27.
Zurück zum Zitat D. Bhattacharjee, A. Chattopadhyay, Delay-optimal technology mapping for in-memory computing using reram devices, in Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, November 7–10 (2016), p. 119 D. Bhattacharjee, A. Chattopadhyay, Delay-optimal technology mapping for in-memory computing using reram devices, in Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, November 7–10 (2016), p. 119
28.
Zurück zum Zitat D. Bhattacharjee, A. Easwaran, A. Chattopadhyay, Area-constrained technology mapping for in-memory computing using reram devices, in Asia and South Pacific Design Automation Conference, ASP-DAC (2017), pp. 1–6 D. Bhattacharjee, A. Easwaran, A. Chattopadhyay, Area-constrained technology mapping for in-memory computing using reram devices, in Asia and South Pacific Design Automation Conference, ASP-DAC (2017), pp. 1–6
Metadaten
Titel
In-Memory Data Compression Using ReRAMs
verfasst von
Debjyoti Bhattacharjee
Anupam Chattopadhyay
Copyright-Jahr
2017
DOI
https://doi.org/10.1007/978-3-319-54840-1_13

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