1. Introduction

In 1965, Gordon Moore predicted that the number of transistors per chip would double every two years and that chips would eventually be so small, that they could be embedded in homes, cars, and mobile devices. As this prophecy came true, the efficient exploitation of the computational performance of such systems is achieved through new resource-aware programming paradigms such as of invasive computing. They introduce novel runtime adaptivity that renders compilation difficult because the actual number of executing processors becomes only known at runtime. This is a challenging task, as a just-in-time compiler on multiprocessor systems-on-chip (MPSoC) is often prohibitive due to the restricted memory available on such devices. Moreover, the possibility of dynamic runtime compilation and optimized code generation might be out of reach for reasons of unacceptable time overheads. Therefore, novel compiler support for adaptive parallel execution of programs on processor arrays such as TCPAS is required. At the same time, it is of utmost importance to take countermeasures against the increasing proneness to errors of modern MPSoCs. In safety-critical environments such as avionics and automotive, single-event upset (SEU) might change the current program behavior either temporally or even permanently. Accordingly, novel adaptive approaches to enable fault tolerance according to environmental conditions and/or application requirements are also needed for parallel program execution, where faults may otherwise propagate over multiple resources.