Full-Chip Nanometer Routing Techniques

verfasst von: Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen

Verlag: Springer Netherlands

Buchreihe : Analog Circuits and Signal Processing

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

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Über dieses Buch

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

As Moore’s Law continues unencumbered into the nanometer era, chips are reaching 1,000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever-increasing design complexity, and be capable of adapting to the constraints of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In this book, we present a multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization.

Chapter 2. Routing Challenges for Nanometer Technology

As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of SIGnal-integrity and MAnufacturing limitations. To meet the signal timing requirements, it is dispensable to address the signal-integrity issues in routing stage. To guarantee yield and reliability, routing for manufacturability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this chapter, we introduce major challenges arising from nanometer process technology and key existing techniques for handling the challenges in routing problems for nanometer technology.

Chapter 3. Multilevel Full-Chip Routing Considering Crosstalk And Performance

In this chapter, we present a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. For performance-driven routing, we use a minimum-radius minimum-cost spanning-tree (MRMCST) heuristic for global routing.

Chapter 4. Multilevel Full-Chip Routing Considering Antenna Effect Avoidance

As technology advances into nanometer territory, the antenna effect problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high-density plasma. Furthermore, the continuous increase of the problem size in IC routing is also a great challenge to existing routing algorithms. In this chapter, we present a framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach.

Chapter 5. Multilevel Full-Chip Routing For The X-Based Architecture

As technology advances into the nanometer territory, the interconnect delay has become a first-order factor on chip performance. To handle this effect, the X-architecture has been proposed for high-performance integrated circuits. The X-architecture presents a new way of orienting a chip’s microscopic interconnect wires with the pervasive use of diagonal routes. It can reduce the wire length and via count, and thus improve performance and routability. Furthermore, the continuous increase of the problem size in IC routing is also a great challenge to existing routing algorithms. In this chapter, we present the first multilevel framework for full-chip routing using the X-architecture. To take full advantage of the X-architecture, we explore the optimal routing for three-terminal nets on the X-architecture and develop a general XST algorithm based on the Delaunay triangulation approach for the X-architecture [55]. The multilevel routing framework adopts a two-stage technique of coarsening followed by uncoarsening, with a trapezoid-shaped track assignment embedded between the two stages to assign long, straight diagonal segments for wire length reduction.

Chapter 6. Concluding Remarks And Future Work

In this chapter, we give concluding remarks and discuss some future research directions. We have presented a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization in this book. To handle both the signal-integrity and manufacturability problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. This intermediate stage not only speeds up the runtime, but also provides a suitable stage for doing optimization. Furthermore, we have adopted this novel multilevel routing framework to consider crosstalk, performance, and antenna effect problems, and the experimental results have shown that our approach is efficient and effective. In order to take advantage of the X-architecture, we also adapt our multilevel routing framework on the X-based architecture. The experimental results show that our approach is capable of handling diagonal segments well.

Backmatter

Titel: Full-Chip Nanometer Routing Techniques
verfasst von: Tsung-Yi Ho
Yao-Wen Chang
Sao-Jie Chen
Verlag: Springer Netherlands
Electronic ISBN: 978-1-4020-6195-0
Print ISBN: 978-1-4020-6194-3
DOI: https://doi.org/10.1007/978-1-4020-6195-0

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