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1999 | Buch

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Flash Memories

verfasst von: Paulo Cappelletti, Carla Golla, Piero Olivo, Enrico Zanoni

Verlag: Springer US

Enthalten in: Professional Book Archive

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A Flash memory is a Non Volatile Memory (NVM) whose "unit cells" are fabricated in CMOS technology and programmed and erased electrically. In 1971, Frohman-Bentchkowsky developed a folating polysilicon gate tran sistor [1, 2], in which hot electrons were injected in the floating gate and removed by either Ultra-Violet (UV) internal photoemission or by Fowler Nordheim tunneling. This is the "unit cell" of EPROM (Electrically Pro grammable Read Only Memory), which, consisting of a single transistor, can be very densely integrated. EPROM memories are electrically programmed and erased by UV exposure for 20-30 mins. In the late 1970s, there have been many efforts to develop an electrically erasable EPROM, which resulted in EEPROMs (Electrically Erasable Programmable ROMs). EEPROMs use hot electron tunneling for program and Fowler-Nordheim tunneling for erase. The EEPROM cell consists of two transistors and a tunnel oxide, thus it is two or three times the size of an EPROM. Successively, the combination of hot carrier programming and tunnel erase was rediscovered to achieve a single transistor EEPROM, called Flash EEPROM. The first cell based on this concept has been presented in 1979 [3]; the first commercial product, a 256K memory chip, has been presented by Toshiba in 1984 [4]. The market did not take off until this technology was proven to be reliable and manufacturable [5].

Inhaltsverzeichnis

Frontmatter

1. Flash Memories: An Overview

Abstract

Solid-state memory devices which retain information once the power supply is switched off are called “nonvolatile” memories. For instance, using standard digital technology, a nonvolatile memory can be implemented by writing permanently the data in the memory array during manufacturing (mask-programmed Read Only Memories, ROM). As an alternative, the user can program the information by blowing fusible links or antifuses, thus changing permanently the cell content (i.e. obtaining a Programmable ROM or PROM). In both cases, the memory array can not be erased, thus making these solutions viable only for a limited number of applications.

Piero Olivo, Enrico Zanoni

2. The Industry Standard Flash Memory Cell

Abstract

This chapter gives a thorough overview of the Industry Standard Flash Memory Cell. More than 85% of today Flash memories rely on this concept. We will describe the basic structure of the floating gate device, and its operating conditions. We will highlight the main differences in the technology and process with respect to a standard CMOS process. Finally, a brief introduction on some of the more important yield and reliability issues will be given.

Paolo Pavan, Roberto Bez

3. Binary and Multilevel Flash Cells

Abstract

The selection of a Flash cell approach is a reflection of the market and product features that a company decides to pursue. There are two major markets for Flash memories: one is the traditional embedded memory, and the other is the new emerging market of mass storage.

Boaz Eitan, Anirban Roy

4. Physical Aspects of Cell Operation and Reliability

Abstract

This chapter overviews the basic physical effects involved in programming and erasing of Flash memory cells, to provide the background for a deeper understanding of their operation and reliability. In particular, tunneling and high field transport are treated and the associated phenomena in MOS-FETs and Flash cells are described by means of measurements and simulations. Device degradation induced by charge injection into thin silicon dioxide layers is also briefly discussed.

Luca Selmi, Claudio Fiegna

5. Memory Architecture and Related Issues

Abstract

In the Flash memory scenario, several different approaches can be found, each one with its characteristics that make each solution more suitable for a particular application. One method to classify these different approaches is to consider the “memory architecture”, i.e. the way in which the array, and consequently the device, is organized.

Maurizio Branchetti, Giovanni Campardo, Stefano Commodaro, Stefano Ghezzi, Andrea Ghilardelli, Carla Golla, Ignazio Martines, Marco Maccarrone, Rino Micheloni, Matteo Zammattio, Stefano Zanardi

6. Multilevel Flash Memories

Abstract

The threshold voltage of a Flash memory transistor depends analogically on the charge amount stored on its floating gate, and if a number m of different threshold levels can be reliably programmed and sensed in a memory cell, this can store n = log₂ m bits, thereby overcoming the traditional one-to-one correspondence between cell count and memory capacity. Multilevel (ML) storage is therefore very attractive, as it allows cost-per-bit reduction for any given fabrication technology. However, to implement ML Flash memories more severe requirements have to be met as compared with the traditional bilevel approach in terms of cell sensing and writing, as well as of reliability.

This chapter reviews the fundamental issues specific of ML Flash memories, with particular regard to the case of stand-alone memories, where the large array size justifies the overhead required to reliably implement the ML concept. The basic features of 4-level multimegabit Flash prototypes presented so far in the literature are illustrated as significant examples of implementation.

Guido Torelli, Massimo Lanzoni, Alessandro Manstretta, Bruno Riccò

7. Flash Memory Reliability

Abstract

With reference to the mainstream technology, the most relevant failure mechanisms which affect yield and reliability of Flash memory are reviewed, showing the primary role played by tunnel oxide defects. The effectiveness of a good test methodology combined with a proper product design for screening at wafer sort latent defects of tunnel oxide is highlighted as key factors for improving Flash memory reliability. The degradation of device performance induced by program/erase cycling is discussed, covering the behavior of a typical cell, the evolution of memory array distribution, and the single bit failure modes. Oxide traps are demonstrated to be responsible for the most critical failure mechanisms, like the erratic erase and the single bit data loss: the impact of stress-induced leakage current on data retention is shown to limit the scalability of tunnel oxide thickness. Finally, reliability implications of multilevel cell concept are briefly analyzed.

Paolo Cappelletti, Alberto Modelli

8. Flash Memory Testing

Abstract

This chapter is not aimed at providing a complete testing theory about Flash; its objective is to present and analyze the most critical aspects related to Flash testing, the tools and methods to improve their testability; to give an idea of the test flow, and of its relation with the excellent quality and reliability that Flash have reached. Aspects related to test cost and productivity are also presented.

The subject is seen from the viewpoint of the Flash manufacturer and treated in very practical terms, with the intent to give an insight into these aspects to the non-expert reader.

Although most of the aspects may be valid for other Flash technologies, this chapter refers to the mainstream Flash technology: NOR architecture, erased by Fowler-Nordheim, programmed by Channel Hot Electrons.

The subjects of testing Known-Good-Die, Flash Cards or embedded Flash are not presented: each one would have required a dedicated chapter.

For the reader interested in a more theoretical and formal insight into Semiconductor Memory testing, excellent books exist (e.g. [1]); for the test engineer with the need to go more deeply in the practical details of Flash testing, exhaustive datasheets and application notes are published by Flash manufacturers.

Giulio Casagrande

9. Flash Memories: Market, Marketing and Economic Challenges

Abstract

We describe in this chapter the dynamics of the Flash memory market, its segmentation and its expected evolution.

The typical characteristic of Flash memory technology, its flexibility, is seen as the main factor which explains the strong evolution of the demand, generating continuous new field application with the typical pervasiveness of the innovative semiconductors.

But the flexibility also determines the peculiar position of this product in the market. The Flash memory does not correspond to our definition of “commodity”, but follows the same price pressure as the big commodity market, represented by DRAM, and dictated by the technology learning curve and by the classical macroeconomic supply/offer models. Flash memories are not a dedicated product, but can, accordingly to the environment, appear sometimes as a standard part, or as an application specific circuit. For all applications, however, Flash always plays a strategic role.

A survey of the many applications presented, with an inside focus from the industry and the point of view of the system designer, is somewhat privileged to give a idea of the many great innovations Flash is making possible.

Bruno Beverina, Philippe Bergé, C. Kunkel, G. Moy, A. Damiano, R. Ferrara, A. Re

Backmatter

Titel: Flash Memories
verfasst von: Paulo Cappelletti
Carla Golla
Piero Olivo
Enrico Zanoni
Verlag: Springer US
Electronic ISBN: 978-1-4615-5015-0
Print ISBN: 978-0-7923-8487-8
DOI: https://doi.org/10.1007/978-1-4615-5015-0

Springer Professional

Über dieses Buch

Inhaltsverzeichnis

Frontmatter

1. Flash Memories: An Overview

2. The Industry Standard Flash Memory Cell

3. Binary and Multilevel Flash Cells

4. Physical Aspects of Cell Operation and Reliability

5. Memory Architecture and Related Issues

6. Multilevel Flash Memories

7. Flash Memory Reliability

8. Flash Memory Testing

9. Flash Memories: Market, Marketing and Economic Challenges

Backmatter