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1999 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Architecture and CAD for Deep-Submicron FPGAS

verfasst von: Vaughn Betz, Jonathan Rose, Alexander Marquardt

Verlag: Springer US

Buchreihe : The International Series in Engineering and Computer Science

Enthalten in: Professional Book Archive

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Über dieses Buch

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools.
Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes.
Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert.
In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues.
Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstarct
Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-architect one’s FPGAs and Computer-Aided Design (CAD) tools. This book addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 2. Background and Previous Work
Abstarct
The first half of this chapter provides background information about FPGA architectures, and briefly describes the prior work relevant to this book. The second half of the chapter describes the CAD flow used to automatically map circuits into FPGAs and determine their speed, and summarizes some of the prior work in the relevant areas of CAD.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 3. CAD Tools: Packing and Placement
Abstarct
This chapter describes the logic block packing tool we developed to target clusterbased logic blocks and the new and novel parts of our FPGA placement tool.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 4. Routing Tools and Routing Architecture Generation
Abstarct
In this chapter we describe how the routing portion of VPR works. We begin by describing the spectrum of FPGA architectures that the router has targeted, and the understandable architecture parameters used to describe an FPGA to VPR. We then explain how a routing architecture is represented internally, and how the succinct description provided by a user is automatically turned into this highly detailed architecture representation. Next, we describe the two routers built into VPR; one is purely routability-driven, while the other is both timing- and routability-driven. The timing-driven router requires a fast and accurate net delay extractor and a path-based timing analyzer, both of which are also discussed. Finally, we compare the performance of VPR to that of several other published CAD tools, and show that it outperforms all the tools to which we have been able to compare.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 5. Global Routing Architecture
Abstarct
In this chapter we investigate which global routing architectures lead to the best FPGA area-efficiency [2, 3]. We use the term global routing architecture to refer to the distribution of routing tracks across an FPGA; that is, the relative number of tracks contained in each channel of the FPGA. In the next section we describe some of the different types of global routing architectures, and explain why this is an important problem in FPGA design. Section 5.2 describes the experimental flow we use to evaluate different global routing architectures — this flow is based on the CAD tools described in Chapters 3 and 4. In Section 5.3 we investigate directionally-biased global routing architectures, in which the channels in the vertical direction have a different width than those in the horizontal direction. Section 5.4 examines non-uniform global routing architectures, which have wider channels in some regions of the FPGA than in others.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 6. Cluster-Based Logic Blocks
Abstarct
In this chapter we investigate the speed and area-efficiency of FPGAs which use logic clusters as their logic block. A logic cluster is composed of several look-up tables and registers interconnected by local routing, as described in Section 3.1.1. In the next section we motivate our research by describing some of the advantages of cluster-based logic blocks, and by showing that these logic blocks are commercially relevant. Section 6.2 describes the experimental flow we use to evaluate different logic clusters. Sections 6.3 through 6.6 then explore several key architectural questions concerning these logic blocks: how many inputs (I) should the FPGA routing provide to each logic cluster; how should the logic block to general routing interface change as a function of logic cluster size (N); and how are circuit speed, FPGA area-efficiency, and design compile time affected by the size of the logic cluster used?
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 7. Detailed Routing Architecture
Abstarct
In this chapter we explore a series of detailed routing architectures to find which ones lead to the best FPGA area and speed [14]. The detailed routing architecture of an FPGA specifies the length of every wire in the FPGA, the type of switch used to make every connection, the switch block topology, the metal width and spacing of each routing wire, and several other related parameters. In the next section we more precisely define all the parameters determining an FPGA’s detailed routing architecture, and explain why detailed routing architecture issues are so crucial in FPGA design. Section 7.2 then describes the experimental flow we use to evaluate different routing architectures.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Chapter 8. Conclusions and Future Work
Abstarct
This work has contributed to two related research areas: FPGA CAD algorithms and FPGA architecture. The new CAD algorithms and tools developed in this research were described in Chapters 3 and 4, and are briefly summarized in Table 8.1. In Chapter 3, we developed the first publicly-described logic block packing tools targeting cluster-based logic blocks.1 We also created a new simulated annealing based placement tool (the placement portion of bur Versatile Place and Route (VPR) program) which incorporates three new enhancements over prior tools. First, we implemented a new annealing schedule that adapts automatically to different placement problems, provides good result quality and is more robust than the schedule of Huang et al [82]. Second, we developed a new, “linear congestion” placement cost function that enhances the routability of circuits mapped to FPGAs in which different channels have different widths. Finally, we developed an incremental net bounding box update algorithm that reduces the CPU time required for placement by more than a factor of five, on average, vs. using the traditional brute-force bounding box recomputation.
Vaughn Betz, Jonathan Rose, Alexander Marquardt
Backmatter
Metadaten
Titel
Architecture and CAD for Deep-Submicron FPGAS
verfasst von
Vaughn Betz
Jonathan Rose
Alexander Marquardt
Copyright-Jahr
1999
Verlag
Springer US
Electronic ISBN
978-1-4615-5145-4
Print ISBN
978-1-4613-7342-1
DOI
https://doi.org/10.1007/978-1-4615-5145-4