Thin Film Ferroelectric Materials and Devices

The DRAM (dynamic random access memory) has been the dominant solid state memory since it was patented in 1967 [1] and first mass marketed as a 4 Kb DRAM by Intel Corporation in 1972 [2]. The success of this memory device over its competitors was its simple and small cell design consisting of one transistor and one capacitor (1T-1C) per bit. A schematic diagram of a DRAM cell and array is shown in Figure 1. Data are stored in an array of capacitors at the intersection of columns of bit lines and rows of word lines. Applying a voltage to one row of word lines turns “on” a row of transistors, allowing a row of capacitors to discharge onto their individual bit lines. During a read operation, a “sense amplifier” at the end of each bit line determines if the capacitor was charged 1 or 0 and then rewrites that charge by applying the appropriate voltage prior to the word line turning “off”. Most DRAMs set the value of the ground electrode of the capacitor to half of the operating voltage of the chip (Vcc) and then a 1 or 0 is stored by applying either Vcc or OV to the capacitor. One advantage of this approach is that the voltage across the capacitor is only +/- Vcc/2. The minimum size of the cell capacitance is determined by the bit line capacitance, the leakage current through the transistor and the cell capacitor, and the charge collected from an α-particle traveling in the Si near the transistor. The α-particles are generated from the decay of naturally occurring isotopes such as Ur which are considered to be contaminants. Since the capacitors lose charge, the cells are recharged using a refresh operation; therefore, DRAM is a volatile memory device.

The memory capacity of the DRAM, a major application of LSI and the technology driving semiconductor devices, has quadrupled every three years. To increase device integration, we must solve not only the engineering problems, such as fine-patterning, microtransistor operation and wiring life, but also the problem of capacitor. The storage unit of a DRAM (cell) consists of a capacitor, which accumulates electric charge, and a switching transistor; accordingly, a certain amount of accumulated electric charge must be ensured to restrict device operation while the cell area is being reduced by miniaturization. To ensure accumulated electric charge sufficient for greater DRAM integration, capacitor dielectric film thickness has been reduced, electrode area has been increased by applying a three-dimensional structure, and capacitor materials have been changed to materials with high dielectric constants (from SiO₂ films to so-called ON films obtained by oxidizing Si₃N₄).

The possibility of the formation of periodic arrangements of 90°-domains in ferroelectric epitaxial films is discussed. Domains can construct a simple alternation of two domains or more complex hierarchical polydomain structures. The physical reason for their formation is a relaxation of the elastic energy of misfit stresses in an epitaxial system. Therefore, they are called elastic domains. The thermodynamic theory of elastic domains predicts architectures of polydomain structures, domain fractions in them, their scales and effect of external mechanical and electrical fields on these characteristics. The theory is supposed to provide a guidance for modeling and engineering polydomain structures in ferroelectric epitaxial heterostructures. Current theoretical and experimental studies on polydomain heterostructures are discussed.

Ferroelectric films can display a wide range of dielectric, ferroelectric, piezoelectric, electrostrictive, and pyroelectric properties. The potential utilization of these properties in a new generation of devices has motivated intensive studies on the synthesis, characterization, and determination of processing-microstructure-property relationships of ferroelectric thin films during the last five years. In addition, there has been an increased drive for integrating ferroelectric film-based heterostructures with different substrate materials to demonstrate devices which exploit the dielectric, ferroelectric, piezoelectric, electrostrictive, and pyroelectric properties of these materials. For example, the high dielectric permittivities of perovskite-type materials can be advantageously used in dynamic random access memories (DRAM),^1-3 while the large values of switchable remanent polarization of ferroelectric materials are suitable for non-volatile ferroelectric random access memories (NVFRAM).^1-3

This chapter is a review of material which in general had been presented earlier by the author in shorter journal articles.¹ It describes particular aspects of an overall paradigm shift in nonvolatile computer memories from silicon-technology based EEPROMs (electrically erasable programmable read-only memories) to devices in which the stored information is coded into + and - polarizations in small (0.7 × 0.7 μm) ceramic thin-film ferroelectrics.^2-5 Such devices have erase/rewrite speeds of 60 ns in commercial embodiments and 0.9 ns in laboratory prototypes, many orders of mangintude faster than the speeds of the best EEPROMs,^6-8 as summarized in Table I. In addition, they may be integrated directly into GaAs circuitry (not just Si devices), where conventional EEPROMs are impossible, due to the different oxidation rates of Ga and As. Fundamental questions concerning aging of performance, however, have delayed full commercialization.^9,10 Because ferroelectrics normally have extremely large dielectric constants, their use as passive elements in computer memories, particularly as non-switching capacitors in DRAMs (dynamic random access memories) is also rapidly evolving.¹¹ Although early prototypes of ferroelectric memories employed many different compounds, including BaMgF₄ and KNO₃, most recent studies have emphasized lead zirconate-titanate (PZT) for nonvolatile memory elements and barium strontium titanate (BST) as DRAM capacitors. These memory devices are part of an even larger family of integrated ferroelectric devices, summarized in Table II, that include lead-scandium tantalate integrated pyroelectric detectors, GaAs MMIC bypass capacitors, and strontium titanate phased array radars, etc.

Ferroelectric thin film semiconductor memories have the potential to dominate world memory markets. Technical developments in the next five years will determine whether ferroelectric thin film memory technology will be the basis of an annual $30 billion market or will be relegated to only niche market status. Among the technologies that ferroelectric random access memories (FERAMs) could replace are electrically erasable programmable read only memories (EEPROMs), Flash nonvolatile memories (FLASH), and dynamic random access memories (DRAMs). Ferroelectric thin film nonvolatile memory technology will be emphasized in this chapter. FERAMs offer advantages of fast write speeds, high endurance and low operating voltage compared to EEPROMs and FLASH technologies. Present FERAM write speeds are approximately two orders of magnitude faster than FLASH and four orders of magnitude faster than EEPROMs. Further, operating voltages are less than 5 volts for FERAMs compared to 12 volt operation for FLASH and EEPROMs. Present FERAM technologies based on Pb(Zr,Ti)O₃ (PZT) with oxide electrodes or SrBi₂Ta₂O₉ (SBT) with Pt electrodes provide in excess of 10¹³ read/write cycles.

For much of its recent history, advances in integrated circuit (IC) technology have been largely the result of a rapid and steady increase in the on-chip circuit element density. This trend is most apparent in the case of volatile digital memories [e.g., dynamic-random-access memory (DRAM)], where the current memory densities are approaching 1 Gbit. This has lead dramatic strides in circuit functionality, compactness, energy efficiency, and reliability. This course to higher integration densities has been driven by both technological and economic forces. However, the cost of this process has been the dramatic decrease in component dimensions and substantial increase in processing complexity in ultra-large-scale-integration (ULSI) of circuits. The performance specifications of ULSI have begun to challenge the ability of conventional IC materials at a fundamental properties level. Consequently, device manufacturers have been forces to consider the integration of “novel” materials into future-generation ICs [1‐3]. In DRAM, for example, as the allowed cell area for the storage-node capacitor continues to decrease, the required storage charge also decreases but at a proportionally slower rate. A current strategy to overcome this problem is to replace the conventional silicon-oxide-nitride-oxide (ONO) layered dielectric with a material with significantly higher dielectric permittivity. For this application, the development of thin-film perovskite-structured oxide dielectrics such as (Ba_xSr_1-x)TiO₃ (BST) has received considerable attention since these materials typically exhibit dielectric permittivities two orders of magnitude higher than that of conventional ONO dielectrics [1‐3]. By incorporating such high-dielectric-constant materials into storage-node capacitor structures, the capacitor area and the number and complexity of the process step required to form it can be decreased [4]. In addition, simple planar- or bumped-capacitor structures can be used as opposed to the complex. ULSI-scale geometries requisite with ONO dielectrics to provide the required capacitor area (thus capacitance) [5].

Ferroelectric perovskite thin films are being developed for a wide range of applications, including nonvolatile memories, high-density DRAMs (≥ 1 Gbit), integrated decoupling capacitors, piezoelectric sensors and actuators, IR detector arrays, and optical switches and modulators. While the fundamental properties (ferroelectric, dielectric, piezoelectric, pyroelectric, and electrooptic) of these materials are well suited to these various applications, the lifetime and reliability of devices is ultimately limited by degradation and aging phenomena [1]. Consequently, there has been extensive research devoted to understanding the mechanisms responsible for the degradation and/or aging of perovskite films with time, temperature, and external field stress [2‐19].

Realization of a commercially viable ferroelectric memory technology has been hampered by one or a combination of problems related to either the reliable performance of the ferroelectric capacitor or to the growth and processing of capacitors that translate to high density memory elements. Issues related to the growth and processing of ferroelectric capacitors have already been discussed at least in part, in earlier chapters. Prior to discussing the reliability issues, a comment on the ferroelectric material is warranted. Currently, there is some debate regarding the choice of ferroelectric material and their associated merits and disadvantages. The two materials of choice are doped or undoped lead zirconate titanate [PZT] and SrBi₂Ta₂O₉. We believe that PZT is the better choice primarily due to the temperature restrictions in Si-CMOS technology and therefore the discussion in this chapter is limited to PZT. We discuss issues related to the reliable performance of lead zirconate titanate [PZT] and cationically substituted derivatives (Pb,La)(Zr,Ti)O₃ [PLZT], Pb(Zr,Ti,Nb)O₃ [PNZT] ferroelectric capacitors. In recent years, it has become clear that the choice of electrode material is very crucial in determining the reliability characteristics of ferroelectric capacitors. Different electrode materials that may be used in conjunction with lead based ferroelectric thin films for non-volatile memory applications have been briefly discussed in an earlier chapter (by Bruce Tuttle). In the following, some of the requirements for a material to be used as an electrode are emphasized.