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2018 | OriginalPaper | Buchkapitel

Formal Verification of a Programmable Hypersurface

verfasst von : Panagiotis Kouvaros, Dimitrios Kouzapas, Anna Philippou, Julius Georgiou, Loukas Petrou, Andreas Pitsillides

Erschienen in: Formal Methods for Industrial Critical Systems

Verlag: Springer International Publishing

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Abstract

A metasurface is a surface that consists of artificial material, called metamaterial, with configurable electromagnetic properties. This paper presents work in progress on the design and formal verification of a programmable metasurface, the Hypersurface, as part of the requirements of the VISORSURF research program (HORIZON 2020 FET-OPEN). The Hypersurface design is concerned with the development of a network of switch controllers that are responsible for configuring the metamaterial. The design of the Hypersurface, however, has demanding requirements that need to be delivered within a context of limited resources. This paper shares the experience of a rigorous design procedure for the Hypersurface network, that involves iterations between designing a network and its protocols and the formal evaluation of each design. Formal evaluation has provided results that, so far, drive the development team in a more robust design and overall aid in reducing the cost of the Hypersurface manufacturing.

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Literatur
2.
Zurück zum Zitat Benini, L., DeMicheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)CrossRef Benini, L., DeMicheli, G.: Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)CrossRef
3.
Zurück zum Zitat Bhargavan, K., Obradovic, D., Gunter, C.A.: Formal verification of standards for distance vector routing protocols. J. ACM 49(4), 538–576 (2002)MathSciNetCrossRef Bhargavan, K., Obradovic, D., Gunter, C.A.: Formal verification of standards for distance vector routing protocols. J. ACM 49(4), 538–576 (2002)MathSciNetCrossRef
4.
Zurück zum Zitat Bloem, R., et al.: Decidability of Parameterized Verification. Morgan and Claypool Publishers, San Rafael (2015) Bloem, R., et al.: Decidability of Parameterized Verification. Morgan and Claypool Publishers, San Rafael (2015)
5.
Zurück zum Zitat Bulychev, P.E., et al.: UPPAAL-SMC: statistical model checking for priced timed automata. In: Proceedings of QAPL 2012, vol. 85. EPTCS, pp. 1–16 (2012) Bulychev, P.E., et al.: UPPAAL-SMC: statistical model checking for priced timed automata. In: Proceedings of QAPL 2012, vol. 85. EPTCS, pp. 1–16 (2012)
6.
Zurück zum Zitat Chawade, S., Gaikwad, M., Patrikar, R.: Review of XY routing algorithm for network-on-chip architecture. Int. J. Comput. Appl. 43, 20–23 (2012) Chawade, S., Gaikwad, M., Patrikar, R.: Review of XY routing algorithm for network-on-chip architecture. Int. J. Comput. Appl. 43, 20–23 (2012)
9.
Zurück zum Zitat Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of DAC 2001, pp. 684–689. ACM (2001) Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of DAC 2001, pp. 684–689. ACM (2001)
10.
Zurück zum Zitat Dombrowski, C., Junges, S., Katoen, J., Gross, J.: Model-checking assisted protocol design for ultra-reliable low-latency wireless networks. In: Proceedings of SRDS 2016, pp. 307–316. IEEE Computer Society (2016) Dombrowski, C., Junges, S., Katoen, J., Gross, J.: Model-checking assisted protocol design for ultra-reliable low-latency wireless networks. In: Proceedings of SRDS 2016, pp. 307–316. IEEE Computer Society (2016)
14.
Zurück zum Zitat Kouvaros, P., Lomuscio, A.: Parameterised verification for multi-agent systems. Artif. Intell. 234, 152–189 (2016)MathSciNetCrossRef Kouvaros, P., Lomuscio, A.: Parameterised verification for multi-agent systems. Artif. Intell. 234, 152–189 (2016)MathSciNetCrossRef
15.
Zurück zum Zitat Li, M., Zeng, Q., Jone, W.: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of DAC 2006, pp. 849–852. ACM (2006) Li, M., Zeng, Q., Jone, W.: DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of DAC 2006, pp. 849–852. ACM (2006)
16.
Zurück zum Zitat Maxemchuk, N.F.: Regular mesh topologies in local and metropolitan area networks. AT&T Tech. J. 64(7), 1659–1685 (1985)CrossRef Maxemchuk, N.F.: Regular mesh topologies in local and metropolitan area networks. AT&T Tech. J. 64(7), 1659–1685 (1985)CrossRef
17.
Zurück zum Zitat Patooghy, A., Miremadi, S.: XYX: a power and performance efficient fault- tolerant routing algorithm for network on chip. In: Proceedings of PDP 2009, pp. 245–251. IEEE Computer Society (2009) Patooghy, A., Miremadi, S.: XYX: a power and performance efficient fault- tolerant routing algorithm for network on chip. In: Proceedings of PDP 2009, pp. 245–251. IEEE Computer Society (2009)
18.
Zurück zum Zitat Sen, K., Viswanathan, M., Agha, G.A.: VESTA: a statistical model-checker and analyzer for probabilistic systems. In: Proceedings of QEST 2005, pp. 251–252. IEEE Computer Society (2005) Sen, K., Viswanathan, M., Agha, G.A.: VESTA: a statistical model-checker and analyzer for probabilistic systems. In: Proceedings of QEST 2005, pp. 251–252. IEEE Computer Society (2005)
19.
Zurück zum Zitat Wu, J.: A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans. Comput. 52(9), 1154–1169 (2003) Wu, J.: A fault-tolerant and deadlock-free routing protocol in 2D meshes based on odd-even turn model. IEEE Trans. Comput. 52(9), 1154–1169 (2003)
20.
Zurück zum Zitat Younes, H.S.: Verification and planning for stochastic processes with asynchrounous events. Ph.D. thesis, Carnegie Mellon University (2004) Younes, H.S.: Verification and planning for stochastic processes with asynchrounous events. Ph.D. thesis, Carnegie Mellon University (2004)
Metadaten
Titel
Formal Verification of a Programmable Hypersurface
verfasst von
Panagiotis Kouvaros
Dimitrios Kouzapas
Anna Philippou
Julius Georgiou
Loukas Petrou
Andreas Pitsillides
Copyright-Jahr
2018
DOI
https://doi.org/10.1007/978-3-030-00244-2_6

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