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Abstract
MPC functionalities are increasingly specified in high-level languages, where control-flow constructions such as conditional statements are extensively used. Today, concretely efficient MPC protocols are circuit-based and must evaluate all conditional branches at high cost to hide the taken branch.
The Goldreich-Micali-Wigderson, or GMW, protocol is a foundational circuit-based technique that realizes MPC for p players and is secure against up to \(p-1\) semi-honest corruptions. While GMW requires communication rounds proportional to the computed circuit’s depth, it is effective in many natural settings.
Our main contribution is \(\mathtt {MOTIF}\) (Minimizing OTs for IFs), a novel GMW extension that evaluates conditional branches almost for free by amortizing Oblivious Transfers (OTs) across branches. That is, we simultaneously evaluate multiple independent\(\mathtt {AND}\) gates, one gate from each mutually exclusive branch, by representing them as a single cheap vector-scalar multiplication (\(\mathtt {VS}\)) gate.
For 2PC with b branches, we simultaneously evaluate up to b\(\mathtt {AND}\) gates using only two 1-out-of-2 OTs of b-bit secrets. This is a factor \(\approx b\) improvement over the state-of-the-art 2b 1-out-of-2 OTs of 1-bit secrets. Our factor b improvement generalizes to the multiparty setting as well: b\(\mathtt {AND}\) gates consume only \(p(p-1)\) 1-out-of-2 OTs of b-bit secrets.
We implemented our approach and report its performance. For 2PC and a circuit with 16 branches, each comparing two length-65000 bitstrings, \(\mathtt {MOTIF}\) outperforms standard GMW in terms of communication by \(\approx \)9.4\(\times \). Total wall-clock time is improved by \(4.1 - 9.2\)\(\times \) depending on network settings.
Our work is in the semi-honest model, tolerating all-but-one corruptions.
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Circuit depth can be reduced by rebalancing at the cost of increased overall circuit size
[BCE91, BB94]. Further, in the 2PC setting, two-input/one-output gates can be aggregated into multi-input/multi-output gates and evaluated in one round at cost exponential in the number of inputs
[KKW17, DKS+17].
Universal circuits (UCs) can be programmed in an online phase to model any circuit up to a given size n. Hence, UCs technically allow GC protocols to precompute a garbling before the circuit topology is known, but at great cost. A UC of size n is implemented with \(3n\log n\) gates
[LYZ+20]. Further, large numbers of GC labels (of total size greater than the garbling of the underlying circuit) must be transferred in the online phase in order to program the UC.