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2017 | OriginalPaper | Buchkapitel

Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives

Applications to AES, PRESENT and SKINNY

verfasst von : Jérémy Jean, Amir Moradi, Thomas Peyrin, Pascal Sasdrich

Erschienen in: Cryptographic Hardware and Embedded Systems – CHES 2017

Verlag: Springer International Publishing

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Abstract

Area minimization is one of the main efficiency criterion for lightweight encryption primitives. While reducing the implementation data path is a natural strategy for achieving this goal, Substitution-Permutation Network (SPN) ciphers are usually hard to implement in a bit-serial way (1-bit data path). More generally, this is hard for any data path smaller than its Sbox size, since many scan flip-flops would be required for storage, which are more area-expensive than regular flip-flops.

In this article, we propose the first strategy to obtain extremely small bit-serial ASIC implementations of SPN primitives. Our technique, which we call bit-sliding, is generic and offers many new interesting implementation trade-offs. It manages to minimize the area by reducing the data path to a single bit, while avoiding the use of many scan flip-flops.

Following this general architecture, we could obtain the first bit-serial and the smallest implementation of AES-128 to date (1560 GE for encryption only, and 1738 GE for encryption and decryption with IBM 130 nm standard-cell library), greatly improving over the smallest known implementations (about 30% decrease), making AES-128 competitive to many ciphers specifically designed for lightweight cryptography. To exhibit the generality of our strategy, we also applied it to the PRESENT and SKINNY block ciphers, again offering the smallest implementations of these ciphers thus far, reaching an area as low as 1065 GE for a 64-bit block 128-bit key cipher. It is also to be noted that our bit-sliding seems to obtain very good power consumption figures, which makes this implementation strategy a good candidate for passive RFID tags.

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Vorheriges Kapitel Four on Embedded Devices with Strong Countermeasures Against Side-Channel Attacks

The same library used to benchmark SIMON area footprints in [5].

We note that the 2400 GE reported in [22] are done on a different library, namely UMC 180 nm. The numbers we report here are obtained by re-synthesizing the code from [22] on IBM 130 nm.

Eight 2-to-1 MUX at the Sbox input are not shown.

It requires four 2-to-1 MUX which are not shown.

Again, necessary 2-to-1 MUX at the inputs are not shown.

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Titel: Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives
verfasst von: Jérémy Jean
Amir Moradi
Thomas Peyrin
Pascal Sasdrich
Verlag: Springer International Publishing
Buch: Cryptographic Hardware and Embedded Systems – CHES 2017
Print ISBN: 978-3-319-66786-7

Electronic ISBN: 978-3-319-66787-4

Copyright-Jahr: 2017
DOI: https://doi.org/10.1007/978-3-319-66787-4_33

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